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ATF1502AS(L)

0995J–PLD–09/02

Figure 1. ATF1502AS Macrocell

Product Terms and

Select Mux

Each ATF1502AS macrocell has five product terms. Each product term receives as its inputs

all signals from both the global bus and regional bus.

The product term select multiplexer (PTMUX) allocates the five product terms as needed to

the macrocell logic gates and control signals. The PTMUX programming is determined by the

design compiler, which selects the optimum macrocell configuration.

OR/XOR/

CASCADE Logic

The ATF1502AS’s logic structure is designed to efficiently support all types of logic. Within a

single macrocell, all the product terms can be routed to the OR gate, creating a 5-input

AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be

expanded to as many as 40 product terms with little additional delay.

The macrocell’s XOR gate allows efficient implementation of compare and arithmetic func-

tions. One input to the XOR comes from the OR sum term. The other XOR input can be a

product term or a fixed high or low level. For combinatorial outputs, the fixed level input allows

polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of

product terms. The XOR gate is also used to emulate T- and JK-type flip-flops.

Flip-flop

The ATF1502AS’s flip-flop has very flexible data and control functions. The data input can

come from either the XOR gate, from a separate product term or directly from the I/O pin.

Selecting the separate product term allows creation of a buried registered feedback within a

combinatorial output macrocell. (This feature is automatically implemented by the fitter soft-

ware). In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flow-

through latch. In this mode, data passes through when the clock is high and is latched when

the clock is low.