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Data Sheet

AD8284

Rev. D | Page 15 of 28

ADC

The AD8284 uses a pipelined ADC architecture. The quantized

output from each stage is combined into a 12-bit result in the

digital correction logic. The pipelined architecture permits the

first stage to operate on a new input sample while the remaining

stages operate on preceding samples. Sampling occurs on the

rising edge of the clock. The output staging block aligns the

data and passes the data to the output buffers.

AUX CHANNEL

The AD8284 allows direct access to the ADC when the mux

settings are used to select the AUX channel. When this channel

is selected, the inputs of the ADC can be accessed using the

INADC+ and INADC− pins. To ensure enough headroom for

full-scale, differential, 2.0 V p-p input signals, bias the INADC±

pins with a 0.9 V common-mode voltage.

CLOCK INPUT CONSIDERATIONS

For optimum performance, clock the AD8284 sample clock

inputs (CLK+ and CLK−) with a differential signal. This signal

is typically ac-coupled into the CLK+ and CLK− pins via a trans-

former or by using capacitors; these pins are biased internally

and require no additional bias.

Figure 17 shows the preferred method for clocking the AD8284.

A low jitter clock source, such as the Valpey Fisher oscillator,

VFAC3-BHL (50 MHz), is converted from single-ended to differ-

ential using an RF transformer. The back-to-back Schottky

diodes across the secondary transformer limit clock excursions

into the AD8284 to approximately 0.8 V p-p differential. This

helps prevent the large voltage swings of the clock from feeding

through to other portions of the AD8284 and preserves the fast

rise and fall times of the signal, which are critical to low jitter

performance.

Figure 17. Transformer-Coupled Differential Clock

If a low jitter clock is available, another option is to ac-couple a

differential PECL or LVDS signal to the sample clock input pins

as shown in Figure 18 and Figure 19. The AD9515/AD9520-0

family of clock drivers offers excellent jitter performance.

Figure 18. Differential PECL Sample Clock

Figure 19. Differential LVDS Sample Clock

In some applications, it is acceptable to drive the sample clock

inputs with a single-ended CMOS signal. In such applications,

drive CLK+ directly from a CMOS gate, and bypass the CLK−

pin to ground with a 0.1 μF capacitor in parallel with a 39 kΩ

resistor (see Figure 20). Although the CLK+ input circuit supply

is via Pin 46, DVDD18CLK, this input is designed to withstand

input voltages of up to 3.3 V, making the selection of the logic

voltage of the driver very flexible. The AD9515/AD9520-0

family of parts can be used to provide 3.3 V inputs (see Figure 21).

In this case, the 39 kΩ resistor is not needed.

Figure 20. Single-Ended 1.8 V CMOS Sample Clock

Figure 21. Single-Ended 3.3 V CMOS Sample Clock

0.1µF

SCHOTTKY

DIODES:

HSM2812

3.3V

50Ω 100Ω

CLK–

CLK+

ADC

AD8284

MINI-CIRCUITS®

ADT1-1WT, 1:1Z

XFMR

VFAC3

OUT

0Ω

0.1µF

240Ω

50Ω*

CLK

50Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

AD8284

PECL DRIVER

3.3V

OUT

VFAC3

AD9515/AD9520-0

0Ω

0.1µF

AD9515/AD9520-0

50Ω*

CLK

50Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

AD8284

LVDS DRIVER

3.3V

OUT

VFAC3

0.1µF

39kΩ

1.8V

CMOS DRIVER

50Ω*

OPTIONAL

100Ω

0.1µF

CLK

50Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

AD8284

3.3V

OUT

VFAC3

AD9515/AD9520-0

0.1µF

CMOS DRIVER

3.3V

50Ω*

OPTIONAL

100Ω

0.1µF

CLK

50Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

AD8284

3.3V

OUT

VFAC3

0.1µF

AD9515/AD9520-0

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