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LTC5100EUF Datasheet(PDF) 31 Page - Linear Technology |
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LTC5100EUF Datasheet(HTML) 31 Page - Linear Technology |
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31 / 52 page  LTC5100 31 sn5100 5100fs OPERATIO Table 3. Example of User ADC Cycle Access READ FROM ADC WRITE TO ADC_USER CYCLE SIGNAL SOURCE Adc_src_sel REGISTER Adc_src Valid Data COMMENT 1T VTERM 0VTERM(1) Selected Signal Source is VTERM 2IM VTERM 0VTERM(1) 3IS VTERM 0VTERM(1) 4 User (VTERM)VTERM 0VTERM(1) 1T VTERM 1VTERM(2) ADC Updates Data with New Data, Setting Valid 2IM VLD VTERM 0VTERM(2) User Selects New Signal Source, VLD, Clearing Valid 3IS VTERM 0VTERM(2) 4 User (VLD)VTERM 0VTERM(2) 1T VLD 1VLD(1) ADC Updates Data with New Data, Setting Vaild and Changing Adc_src to Reflect the Source of the New Data 2IM VLD 1VLD(1) 3IS VLD VLD 0VLD(1) User Reads the ADC_USER Register, Clearing Valid 4 User (VLD)VLD 0VLD(1) 1T VLD 1VLD(2) ADC Updates Data with New Data, Setting Valid 2IM VLD 1VLD(2) 3IS VLD 1VLD(2) 4 User (VLD)VLD 1VLD(2) to Use It, V1.0” by Philips Semiconductor. The 7-bit I2C bus address for the LTC5100 is 0x0A (hex). When the Read/Write bit that follows is a “1”, the resulting 8-bit word becomes 0x15. When the Read/Write bit is a “0”, the 8-bit word becomes 0x14. To communicate with the LTC5100, the bus master transmits the LTC5100 address followed by a command byte and data as defined by the I2C bus specification and shown in Figure 28 and Table 4. Note that 16 bits of data are always transmitted, low byte first, high byte last. Within each transmitted byte, the bit order is Figure 28. I2C Serial Read/Write Sequences (LTC5100 Responses are Shown in Bold Italics) Table 4. Legend for the I2C Protocol SYMBOL MEANING S Start W Write R Read A Acknowledge NA No Acknowledge P Stop S WRITE READ W A LTC5100 ADDRESS (7 BITS) 0x0A COMMAND BYTE LOW BYTE A A HIGH BYTE A P LOW BYTE A HIGH BYTE N A P 5100 F28 SW A LTC5100 ADDRESS (7 BITS) 0x0A LTC5100 ADDRESS 0x0A COMMAND BYTE S A A R MSB .. LSB. The register set and I2C command set for the LTC5100 are documented in Table 7 through Table 30. |
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