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PV88080 Datasheet(PDF) 21 Page - Dialog Semiconductor |
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PV88080 Datasheet(HTML) 21 Page - Dialog Semiconductor |
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21 / 102 page  PV88080 High Efficiency Advanced Feature 4-Channel PMIC Datasheet Revision 1.0 13-Jun-2017 CFR0011-120-00 21 of 102 © 2017 Dialog Semiconductor 3.3.11 Fault Condition A fault condition is generated by: An over temperature event, An under voltage of the 5 V supply If a fault condition is detected the chip will signal an alert to the other chip, then follow its power down sequence without waiting for the other chip. At the end of the power down sequence the chip moves to the RESET state. In the RESET state the registers, apart from the fault log, are reset and the OTP is reloaded at start- up. Table 15: Electrical Characteristics VDD = 4.75 to 5.25 V Parameter Description Conditions Min Typ Max Unit VDD Supply voltage 4.75 5.25 V VDD_FLT _UPPER VDD fault upper 4.5 V VDD_FLT _LWR VDD fault lower 4.4 V VDD_FLT_CRIT VDD fault critical 4.2 V 3.3.12 Digital I/O Signals Standby Pin (STBY) The STBY pin is an input which controls the power up sequence of a system containing PV88080. If STBY=0 the power up sequence is followed to ACTIVE mode. If STBY=1 the power down sequence is followed to STANDBY mode. STBY should be 0 at power up so that the system boots when power is applied. Interrupt Request (nIRQ) The nIRQ is an active low output signal which indicates that an interrupt causing event has occurred and status information is available in the related registers. Such information can be temperature, voltage and over current fault conditions. When an event bit is set the nIRQ signal is asserted (unless masked by a bit in the IRQ mask register), the nIRQ is not released until the event registers have been cleared by writing to the related register with an assigned ‘1’ for the bit to be cleared. The event registers should be written in PAGE/REPEATED mode because the nIRQ is not cleared until all registers with an asserted event have been reset. New events that occur during writing to the registers are held until all the event registers have been written. Then they are passed to the event register, ensuring the SOC does not miss them. There are also some reserved options for the digital pins function/definition which are programmable by the OTP memory. Table 16 shows the list of the options, and the functionality can be realized for different applications with proper role combinations of the pins. |
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