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PV88090

High Efficiency 3-Channel Buck Converter with dual LDO

Datasheet

Revision 1.0

10-Dec-2017

CFR0011-120-00

21 of 42

Via control WRITE_MODE a repeated write mode can be enabled. In this mode, the master can

execute back-to-back write operations to non-consecutive addresses. This is achieved by

transmitting register address and data pairs. The data will be stored in the address specified by

preceding byte. The repeated write mode is illustrated in Figure 9.

SLAVEadr W A

REGadr

DATA

S = START condition

A = Acknowledge (low)

Sr = Repeat START condition

* = No Acknowledge

P = STOP condition

W = Write (low)

R = Read (high)

Master to Slave

Slave to Master

7-bits

1 bit

8-bits

REGadr

1-bit

8-bits

DATA

……….

8-bits

Repeated writes

Figure 9: I2C Repeated Write

If a new START or STOP condition occurs within a message, the bus will return to IDLE-mode.

6.1.9

Dynamic Voltage Control

All buck converters can be controlled by DVC. The buck converters feature a voltage ramping feature

that enables smooth transition from one voltage setting to another.

All output voltages can be controlled with SW via the I2C interface (VBUCK<x>). The I2C interface is

operational when the device is in active mode.

6.2

LDOs

All LDOs employ Dialog Se

miconductor’s Smart Mirror dynamic biasing technology, see Figure 10,

the illustrator which maintains high performance over a wide range of operating conditions and a

power saving mode (sleep mode) to minimize the quiescent current during very low output current.

The circuit technique offers significantly higher gain bandwidth performance than conventional

designs, enabling higher power supply rejection performance at higher frequencies. PSRR is

maintained across the full operating current range however quiescent current consumption is scaled

to demand providing improved efficiency when current demand is low.

Figure 10: Smart MirrorTM Voltage Regulator

LDO1 provides the analog 1.05 V supply voltage (or 1.2 V depending on the system).To limit power

dissipation the input voltage to LDO1 is the DDR voltage, typically 1.5 V.In standby mode the DDR

voltage availability is not guaranteed. Therefore, the input voltage to the LDO switches to VDLDO2

during standby. The current in standby mode is reduced to 100 mA. During standby mode the output

stage from VDLDO1 must be disabled such that reverse current does not flow from VDLDO2 to

VDLDO1 (requires bulk switch on P-channel).

Vout

Cout

ESR

Vin

Smart Mirror

TM LDO

Vref

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