TC581282AXB

2001-12-04

13/31

PIN FUNCTIONS

The device is a serial access memory which utilizes time-sharing input of address information. The device pin-outs

are configured as shown in Figure 1.

Command Latch Enable: CLE

The CLE input signal is used to control loading of

the operation mode command into the internal

command register. The command is latched into the

command register from the I/O port on the rising edge

of the WE signal while CLE is High.

Address Latch Enable: ALE

The ALE signal is used to control loading of either

address information or input data into the internal

address/data register.

Address information is latched on the rising edge of

WE if ALE is High.

Input data is latched if ALE is Low.

Chip Enable:

The device goes into a low-power Standby mode when CE goes High during a wait state. The CE signal is

ignored when device is in Busy state (

BY

/

RY

= L), such as during a Program or Erase or Read operation, and

will not enter Standby mode even if the CE input goes High..

Write Enable:

The WE signal is used to control the acquisition of data from the I/O port.

Read Enable:

The internal column address counter is also incremented (Address = Address + l) on this falling edge.

I/O Port: I/O1 to 8

The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from the

device.

Write Protect:

The WP signal is used to protect the device from accidental programming or erasing. The internal voltage

regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off

sequence when input signals are invalid.

Ready/Busy:

The

BY

/

RY

output signal is used to indicate the operating condition of the device. The

BY

/

RY

signal is in

Busy state (

BY

/

RY

= L) during the Program, Erase and Read operations and will return to Ready state

(

BY

/

RY

= H) after completion of the operation. The output buffer for this signal is an open drain.

1

2

3

4

5

6

7

8

A

NC

NC

B

NC

NC

C

NU

CLE

NU

NU

NU

NU

D

NU

ALE

NU

NU

NU

NU

E

WP

WE

NU

NU

NU

GND

F

NU

NU

NU

NU

NU

NU

G

NU

NU

NU

NU

BY

/

RY

NU

H

CE

I/O1

I/O3

NU

NU

NU

J

RE

NU

NU

I/O8

I/O7

K

I/O2

I/O4

I/O6

I/O5

NC

L

NC

NC

M

NC

NC

CE

WE

RE

WP

BY

/

RY

Figure1. Pinout