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TS81102G0 Datasheet(PDF) 2 Page - ATMEL Corporation |
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TS81102G0 Datasheet(HTML) 2 Page - ATMEL Corporation |
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2 / 38 page  2 TS81102G0 2105C–BDC–11/03 Block Diagram Figure 1. Block Diagram B 2 Counter (8 stage shift register) DataReady generation Data Path Clock Path mux Port Selection Clock Data Output Clock Even Ports Odd Ports mux delay delay even master latch even slave latch odd master latch odd slave latch 8/10 8 Counter NAP 8/10 Status ClkPar 8 8 1 DR/DR FS/8 FS/8 BIST 8/10 Phase control RstGen Reset |
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