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CY28548 Datasheet(PDF) 21 Page - Silicon Laboratories

Part # CY28548
Description  Clock Generator for Intel짰Crestline Chipset
PDF  31 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

CY28548 Datasheet(HTML) 21 Page - Silicon Laboratories

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CY28548
......................Document #: 001-08400 Rev ** Page 21 of 30
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Table 6. Output Driver Status during PCI-STOP# and CPU-STOP#
PCI_STOP# Asserted
CPU_STOP# Asserted
SMBus OE Disabled
Single-ended Clocks
Stoppable
Driven low
Running
Driven low
Non stoppable
Running
Running
Differential Clocks
Stoppable
Clock driven high
Clock driven high
Clock driven Low or 20K
pulldown
Clock# driven low
Clock# driven low
Non stoppable
Running
Running
Table 7. Output Driver Status
All Single-ended Clocks
All Differential Clocks except
CPU1
CPU1
w/o Strap
w/ Strap
Clock
Clock#
Clock
Clock#
Latches Open State
Low
Hi-z
Low or 20K pulldown
Low
Low or 20K pulldown Low
Powerdown
Low
Hi-z
Low or 20K pulldown
Low
Low or 20K pulldown Low
M1
Low
Hi-z
Low or 20K pulldown
Low
Running
Running
Table 8. PLL3/SE Configuration Table
GCLK_SEL
B1b4
B1b3
B1b2
B1b1
Pin 27 (17) MHz Pin 25 (18) MHz Spread (%)
Comment
0
0000
PLL3 Disabled
0
0001
100
100
0.5
SRC1 from SRC_Main
0
0010
100
100
0.5
LCD_100 from PLL3
0
0011
100
100
1
LCD_100 from PLL3
0
0100
100
100
1.5
LCD_100 from PLL3
0
0101
100
100
2
LCD_100 from PLL3
0
0110
N/A
N/A
N/A
N/A
0
0111
N/A
N/A
N/A
N/A
0
1000
N/A
N/A
N/A
N/A
0
1001
N/A
N/A
N/A
N/A
0
1010
N/A
N/A
N/A
N/A
0
1011
N/A
N/A
N/A
N/A
0
1100
N/A
N/A
none
N/A
0
1101
N/A
N/A
N/A
N/A
0
1110
N/A
N/A
N/A
N/A
0
1111
N/A
N/A
N/A
N/A
1
0000
N/A
N/A
N/A
1
0001
27M_NSS
27M_NSS
0.5
27M_NSS from PLL3
1
0010
27M_NSS
27M_NSS
0.5
27M_NSS from PLL3
1
0011
27M_NSS
27M_NSS
1
27M_NSS from PLL3
1
0100
27M_NSS
27M_NSS
1.5
27M_NSS from PLL3
1
0101
27M_NSS
27M_NSS
2
27M_NSS from PLL3
1
0110
N/A
N/A
N/A
1
0111
N/A
N/A
N/A
1
1000
N/A
N/A
N/A
1
1001
N/A
N/A
N/A
1
1010
N/A
N/A
N/A
1
1011
N/A
N/A
N/A
1
1100
N/A
N/A
N/A



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