SL28SRC02

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Pin Definitions

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

clock output buffers are individually enabled or disabled. The

registers associated with the Serial Data Interface initialize to

their default setting at power-up. The use of this interface is

optional. Clock device register changes are normally made at

system initialization, if any are required. The interface cannot

be used during system operation for power management

functions.

Data Protocol

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operations from the controller. For

block write/read operation, Access the bytes in sequential

order from lowest to highest (most significant bit first) with the

ability to stop after any complete byte is transferred. For byte

write and byte read operations, the system controller can

access individually indexed bytes. The offset of the indexed

byte is encoded in the command code described in Table 1.

The block write and block read protocol is outlined in Table 2

while Table 3 outlines byte write and byte read protocol. The

slave receiver address is 11010010 (D2h)

.

Pin No.

Name

Type

Description

1

VDD

PWR 3.3V Power supply

2

SDATA

I/O

SMBus compatible SDATA.

3

SCLK

I

SMBus compatible SCLOCK.

4

VDD

PWR 3.3V power supply

5

VSS

GND

Ground

6

VDD

PWR 3.3V power supply

7

VSS

GND

Ground

8

SRC1

O, DIF 100 MHz Differential serial reference clocks.

9

SRC1#

O, DIF 100 MHz Differential serial reference clocks.

10

VSS

GND

Ground

11

SRC2

O, DIF 100 MHz Differential serial reference clocks.

12

SRC2#

O, DIF 100 MHz Differential serial reference clocks.

13

VDD

PWR 3.3V power supply

14

VDD

PWR 3.3V power supply

15

VSS

GND

Ground

16

VDD

PWR 3.3V power supply

17

SSON

I

3.3V LVTTL input for enabling spread spectrum clock

0 = Disable, 1 = Enable (-0.5% SS)

External 10K ohm pull-up or pull-down resistor required

18

VSS

GND

Ground

19

XOUT

O, SE 14.318 MHz Crystal output.

20

XIN

I

14.318 MHz Crystal input.

Table 1. Command Code Definition

Bit

Description

7

0 = Block read or block write operation, 1 = Byte read or byte write operation

(6:0)

Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'