SL28541BZCT datasheet(5/31 Pages) SILABS

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SL28541

........................ DOC #: SP-AP-0063 (Rev. AA) Page 5 of 31

CPU#0

O, DIF Differential CPU clock outputs.

CPU0

O, DIF Differential CPU clock outputs.

VDD_CPU

PWR

3.3V Power supply for CPU PLL.

CKPWRGD/PD#

3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B,

FS_C, FS_D, SRC5_SEL, and ITP_EN.

After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for

asserting power down (active LOW).

FSB/TEST_MODE

3.3V tolerant input for CPU frequency selection.

Selects Ref/N or Tri-state when in test mode

0 = Tri-state, 1 = Ref/N.

Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.

64 QFN Pin Definitions (continued)

Pin No.

Name

Type

Description

64 TSSOP Pin Definition

Pin No.

Name

Type

Description

PCI0/OE#_0/2_A

I/O, SE 3.3V, 33MHz clock/3.3V OE# Input mappable via I2C to control either SRC0 or

SRC2. (Default PCI0, 33MHz clock)

VDD_PCI

PWR

3.3V Power supply for PCI PLL.

PCI1/OE#_1/4_A

I/O, SE 3.3V, 33MHz clock/3.3V OE# Input mappable via I2C to control either SRC1 or

SRC4. (Default PCI1, 33MHz clock)

PCI2/TME

I/O, SE 3.3V tolerance input for overclocking enable pin/3.3V, 33MHz clock.

(Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications)

PCI3

O, SE, 33 MHz clock.

PCI4 / GCLK_SEL

I/O, SE 33 MHz clock output/3.3V-tolerant input for selecting graphic clock source on pin

13, 14, 17and 18

Sampled on CKPWRGD assertion

PCIF_0/ITP_EN

I/O, SE 3.3V LVTTL input to enable SRC8 or CPU2_ITP/33 MHz clock output. (sampled

on the CK_PWRGD assertion)

1 = CPU2_ITP, 0 = SRC8

VSS_PCI

GND

Ground for outputs.

VDD_48

PWR

3.3V Power supply for outputs and PLL.

USB_48/FSA

I/O

3.3V tolerant input for CPU frequency selection/fixed 3.3V, 48MHz clock output.

(Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications)

VSS_48

GND

Ground for outputs.

VDD_IO

PWR

0.7V Power supply for outputs.

SRC0/DOT96

O, DIF 100MHz Differential serial reference clocks/Fixed 96MHz clock output.

(Selected via I2C default is SRC0)

SRC0#/DOT96#

O, DIF 100MHz Differential serial reference clocks/Fixed 96MHz clock output.

(Selected via I2C default is SRC0)

VSS_IO

GND

Ground for PLL2.

VDD_PLL3

PWR

3.3V Power supply for PLL3

GCLK_SEL

Pin13

Pin14

Pin17

Pin 18

DOT96T DOT96C SRC1T/LCD_100T SRC1C/LCD_100C

SRCT0

SRCC0

27M_NSS

27M_SS

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