W158

..... Document #: 38-07164 Rev. *A Page Page 6 of 12 of 12

Notes:

23. All internal timing is referenced to the CPU clock.

24. PCI_STOP# signal is an input signal that must be made synchronous to PCI_F output.

25. All other clocks continue to run undisturbed.

26. PWRDWN# and CPU_STOP# are shown in a HIGH state.

27. PWRDWN is an asynchronous input and metastable conditions could exist. This signal must be synchronized.

28. The shaded Sections on the VCO and the Crystal signals indicate an active clock.

CPU

PCI

PCI_STOP#

PWRDWN#

PCI_F

(external)

HI

HI

(internal)

PCI

(external)

CPU_STOP#

CPU

PCI

PWRDWN#

VCO

Crystal

PCI

CPU

(internal)

(internal)

(external)

(external)