CYRF8935

Document Number: 001-61351 Rev. *K

Page 21 of 40

Register Definitions

The following registers are accessed using the SPI protocol.

Some of the internal registers and bit fields are not intended for end-user adjustment. Such registers are not described here and

should not be altered from the factory-recommended value

Table 10. RF Register Information

Bit No.

Bit Name

Description

Register 3 – Read only

15:13

(Reserved)

(Reserved)

12

RF_SYNTH_LOCK

Indicates the phase lock status of RF synthesizer.

1: Locked

0: Unlocked

11:0

(Reserved)

(Reserved)

Register 6 – Read only

15:10

RAW_RSSI[5:0]

Indicates 6-bit raw RSSI value from analog circuit.

Each LSB is approximately 1 dB. See Reading

RSSI on page 14 for details.

9:0

(Reserved)

(Reserved)

Register 7

15:9

(Reserved)

(Reserved)

8

TX_EN

Initiates the transmit sequence for state machine

control.

Note that TX_EN and RX_EN cannot be set to ‘1’

at the same time.

7

RX_EN

Initiates the receive sequence for state machine

control.

Note that TX_EN and RX_EN cannot be set to ‘1’

at the same time.

6:0

RF_PLL_CH_NO [6:0]

Sets Tx and Rx RF channel number, for example:

Write 0 for channel 0 (2402 MHz)

Write 39 for channel 39 (2441 MHz)

Write 78 for channel 78 (2480 MHz)

Register 9

15:11

(Reserved)

(Reserved)

10:7

PA_GN[3:0]

PA power level control

6:0

(Reserved)

(Reserved)

Register 10

15:1

(Reserved)

(Reserved)

0

XTAL_OSC_EN

1: Enable crystal oscillator gain block

0: Disable crystal oscillator gain block

15:1

(Reserved)

(Reserved)

Register 11

15

CW_MODE

1: Disables Tx modulation; CW only.

0: Normal Tx mode

14:10

(Reserved)

(Reserved)

9

RSSI_DIS

1: Disable RSSI

0: RSSI operates normally.

8:0

(Reserved)

(Reserved)