CYW43362 datasheet(39/51 Pages) CYPRESS

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Document No. 002-14779 Rev. *H

Page 39 of 51

CYW43362

12. Internal Regulator Electrical Specifications

Note: Values in this document are design goals and are subject to change based on the results of device characterization.

Functional operation is not guaranteed outside the specification limits provided in this section.

12.1 Core Buck Regulator

The specifications for the Core Buck regulator (CBUCK) are provided in Table 18.

Table 18. Core Buck Regulator

Specification

Notes

Minimum

Typical

Maximum

Units

Input supply voltage

–

2.3

–

4.8a

Volts

PWM mode switching

frequency

–

2.56

3.2

3.84

MHz

PWM output current

–

500

Output current limit

–

700

–

Output voltage range

Programmable, 33.33 mV steps

default = 1.8V

1.2

–

1.833

Volts

Output voltage DC accuracy

Includes load and line regulation. VBAT = 2.7V to 4.8V, Load

0 to 500 mA, Inductor DCR < 137.5 mΩ

–5

–

PWM ripple voltage, staticb

Measure with 20 MHz BW limit.

Fixed load (0 to 500 mA).

Max ripple based on VBAT < 4.3V, Vout = 1.833V, Fs = 3.2

MHz, 1.5 µH inductor L > 0.6144 µH, Cap+Board total-ESR

< 10 mΩ, Cout > 1.9 µF

–

mVpp

PWM load step transient

voltage error

VBAT = 2.7V to 4.8V,

current step = 150 to 400 mA,

1 µsec rise-time based on 0402, 6.3V,

X5R, and 4.7 µFc ceramic capacitor.

–

100

200

PWM line step

transient voltage error

VBAT step from 2.3 to 2.7V,

10 µsec rise-time,

fixed 500 mA load based on 0402, 6.3V,

X5R, and 4.7 µFb ceramic capacitor.

–

100

PWM load regulationa

VBAT = 2.7V to 4.8V,

10 mA to 500 mA load.

Inductor DCR < 137.5 mΩ

–

+30

PWM line regulationa

VBAT = 2.7V to 4.8V,

500 mA load.

Inductor DCR < 137.5 mΩ

–

+10

Burst mode ripple voltage, static Load < 30 mA.

Measure with 20 MHz BW limit.

–

mVpp

30 mA < Load < 200 mA.

Measure with 20 MHz BW limit.

–

200

mVpp

Burst mode load step transient

voltage error

VBAT = 2.7V to 4.8V,

current step 10 to 200 mA,

1 µsec rise-time based on 0402, 6.3V,

X5R, and 4.7 µFb ceramic capacitor.

–

120

Burst mode line step transient

voltage error

VBAT step from 2.3V to 2.7V,

10 µsec rise-time, fixed 200 mA load based on 0402, 6.3V,

X5R, and 4.7 µFb ceramic capacitor.

–

100

Burst mode load regulation

VBAT = 2.7V to 4.8V,

10 mA to 200 mA load

–

Burst line regulation

Input voltage 2.7 to 4.8V, 200 mA load

–

Peak PWM mode efficiencyd

200 mA load current

30 mA load current

–

Burst mode efficiency

5 mA load current

–

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