CYW43903 datasheet(8/65 Pages) CYPRESS

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Document Number: 002-14826 Rev. *G

Page 8 of 65

PRELIMINARY

CYW43903

2. Power Supplies and Power Management

2.1 Power Supply Topology

One core buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW43903. All

regulators are programmable via the PMU. These blocks simplify power supply design for application and WLAN functions in

embedded designs.

A single VBAT (3.0V to 4.8V DC maximum) and VIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided

by the regulators in the CYW43903.

The REG_ON control signal is used to power up the regulators and take the appropriate sections out of reset. The CBUCK, CLDO,

LNLDO, and other regulators power up when any of the reset signals are deasserted. All regulators are powered down only when

REG_ON is deasserted. The regulators may be turned off/on based on the dynamic demands of the digital baseband.

The CYW43903 provides a low power-consumption mode whereby the CBUCK, CLDO, and LNLDO regulators are shut down. When

in this state, the low-power linear regulator (LPLDO1) supplied by the system VIO supply provides the CYW43903 with all required

voltages.

2.2 CYW43903 Power Management Unit Features

The CYW43903 supports the following Power Management Unit (PMU) features:

■ VBAT to 1.35Vout (550 mA maximum) core buck (CBUCK) switching regulator

■ VBAT to 3.3Vout (450 mA maximum) LDO3P3

■ 1.35V to 1.2Vout (350 mA maximum) CLDO with bypass mode for deep-sleep

■ 1.35V to 1.2Vout (55 mA maximum) LDO for BBPLL

■ Additional internal LDOs (not externally accessible)

■ PMU internal timer auto-calibration by the crystal clock for precise wake-up timing from the low power-consumption mode.

Figure 3 and Figure 4 show the regulators and a typical power topology.

CYW43903 Datasheet(PDF) 8 Page - Cypress Semiconductor