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MB9B500B Datasheet(PDF) 39 Page - Cypress Semiconductor

Part # MB9B500B
Description  32-bit Arm짰 Cortex짰-M3 FM3 Microcontroller
PDF  115 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

MB9B500B Datasheet(HTML) 39 Page - Cypress Semiconductor

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Document Number: 002-05607 Rev. *E
Page
39 of 115
MB9B500B Series
Module
Pin name
Function
Pin No.
LQFP-100
BGA-112
LQFP-120
Reset
INITX
External Reset Input. A reset is valid when INITX=L.
38
K4
43
Mode
MD0
Mode 0 pin.
During normal operation, MD0=L must be input. During
serial programming to flash memory, MD0=H must be
input.
47
L8
57
MD1
Mode 1 pin. Input must always be at the "L" level.
46
K9
56
Power
VCC
Power Pin.
1
B1
1
VCC
26
J1
31
VCC
35
K1
40
VCC
51
K11
61
VCC
76
A10
91
USBVCC
3.3V Power supply port for USB I/O.
97
A4
117
GND
VSS
GND Pin.
-
B2
-
VSS
25
L1
30
VSS
-
K2
-
VSS
-
J3
-
VSS
-
H4
-
VSS
34
L4
39
VSS
50
L11
60
VSS
-
K10
-
VSS
-
J9
-
VSS
-
H8
-
VSS
-
B10
-
VSS
-
C9
-
VSS
75
A11
90
VSS
-
D8
-
VSS
-
D4
-
VSS
-
C3
-
VSS
100
A1
120
Clock
X0
Main clock (oscillation) input pin.
48
L9
58
X0A
Sub clock (oscillation) input pin.
36
L3
41
X1
Main clock (oscillation) I/O pin.
49
L10
59
X1A
Sub clock (oscillation) I/O pin.
37
K3
42
CROUT
Built-in High-speed CR-osc clock output port.
74
C10
89
Analog
Power
AVCC
A/D converter analog power pin.
60
H11
70
AVRH
A/D converter analog reference voltage input pin.
61
F11
71
Analog
GND
AVSS
A/D converter GND pin.
62
G11
72
C-pin
C
Power stabilization capacity pin.
33
L2
38
Note:
−
While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant
to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in
other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.



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