COP411C datasheet(13/20 Pages) NSC

13 / 20 page

Description of Selected

Instructions

The following information is provided to assist the user in

understanding the operation of several unique instructions

and to provide notes useful to programmers in writing

COP410C411C programs

XAS INSTRUCTION

XAS (Exchange A with SIO) exchanges the 4-bit contents of

the accumulator with the 4-bit contents of the SIO register

The contents of SIO will contain serial-inserial-out shift reg-

ister or binary counter data depending on the value of the

EN register An XAS instruction will also affect the SK out-

put (See Functional Description EN Register) If SIO is se-

lected as a shift register an XAS instruction must be per-

formed once every four instruction cycle times to effect a

continuous data stream

JID INSTRUCTION

JID (Jump Indirect) is an indirect addressing instruction

transferring program control to a new ROM location pointed

to indirectly by A and M It loads the lower eight bits of the

ROM address register PC with the contents of ROM ad-

dressed by the 9-bit word PC8 A M PC8 is not affected by

this instruction

Note

JID uses two instruction cycles if executed one if skipped

LQID INSTRUCTION

LQID (Load Q Indirect) loads the 8-bit Q register with the

contents of ROM pointed to by the 9-bit word PC8 A M

LQID can be used for table look-up or code conversion such

as BCD to 7-segment The LQID instruction ‘‘pushes’’ the

stack (PC a 1

x SA x SB) and replaces the least

significant eight bits of the PC as follows A

x PC74

RAM(B)

x PC30 leaving PC8 unchanged The ROM data

pointed to by the new address is fetched and loaded into

the Q latches Next the stack is ‘‘popped’’ (SB

x SA x

PC) restoring the saved value of the PC to continue se-

quential program execution Since LQID pushes SA

SB the previous contents of SB are lost

Note

LQID uses two instruction cycles if executed one if skipped

INSTRUCTION SET NOTES

a The first word of a COP410C411C program (ROM ad-

dress 0) must be a CLRA (Clear A) instruction

b Although skipped instructions are not executed one in-

struction cycle time is devoted to skipping each byte of

the skipped instruction Thus all program paths take the

same number of cycle times whether instructions are

skipped or executed (except JID and LQID)

c The ROM is organized into eight pages of 64 words

each The program counter is a 9-bit binary counter and

will count through page boundaries If a JP JSRP JID or

LQID instruction is located in the last word of a page the

instruction operates as if it were in the next page For

example A JP located in the last word of a page will

jump to a location in the next page Also a LQID or JID

located in the last word in page 3 or 7 will access data in

the next group of four pages

POWER DISSIPATION

The lowest power drain is when the clock is stopped As the

frequency increases so does current Current is also lower

at lower operating voltages Therefore to minimize power

consumption the user should run at the lowest speed and

voltage that his application will allow The user should take

care that all pins swing to full supply levels to ensure that

outputs are not loaded down and that inputs are not at

some intermediate level which may draw current Any input

with a slow rise or fall time will draw additional current A

crystal- or resonator-generated clock will draw additional

current An RC oscillator will draw even more current since

the input is a slow rising signal

If using an external squarewave oscillator the following

equation can be used to calculate the COP410C current

drain

Ic e Iq a (V c 20 c Fi) a (V c 1280 c FlDv)

where Ic e chip current drain in microamps

Iq e quiescent leakage current (from curve)

Fl e CKI frequency in megahertz

V e chip VCC in volts

Dv e divide by option selected

For example at 5V VCC and 400 kHz (divide by 4)

Ic e 10 a (5 c 20 c 04) a (5 c 1280 c 044)

Ic e 10 a 40 a 640 e 690 mA

IO OPTIONS

COP410C411C outputs have the following optional config-

urations illustrated in

Figure 7

a Standard A CMOS push-pull buffer with an N-channel

device to ground in conjunction with a P-channel device

to VCC compatible with CMOS and LSTTL

b Low Current This is the same configuration as (a) above

except that the sourcing current is much less

c Open Drain An N-channel device to ground only allow-

ing external pull-up as required by the user’s application

d Standard TRI-STATE L Output A CMOS output buffer

similar to (a) which may be disabled by program control

e Low-Current TRI-STATE L Output This is the same as

(d) above except that the sourcing current is much less

Open-Drain TRI-STATE L Output This has the N-chan-

nel device to ground only

The SI and RESET inputs are Hi-Z inputs (

Figure 7g )

When using either the G or L IO ports as inputs a pull-up

device is necessary This can be an external device or the

following alternative is available Select the low-current out-

put option Now by setting the output registers to a logic

‘‘1’’ level the P-channel devices will act as the pull-up load

Note that when using the L ports in this fashion the Q regis-

ters must be set to a logic ‘‘1’’ level and the L drivers

must

be enabled by an LEI instruction

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