M48Z35 datasheet(10/20 Pages) STMICROELECTRONICS

10 / 20 page

M48Z35, M48Z35Y

10/20

WRITE Mode

The M48Z35/Y is in the WRITE Mode whenever W

and E are low. The start of a WRITE is referenced

from the latter occurring falling edge of W or E.A

WRITE is terminated by the earlier rising edge of

W or E. The addresses must be held valid through-

out the cycle. E or W must return high for a mini-

mum of tEHAX from Chip Enable or tWHAX from

WRITE Enable prior to the initiation of another

READ or WRITE cycle. Data-in must be valid tD-

VWH prior to the end of WRITE and remain valid for

tWHDX afterward. G should be kept high during

WRITE cycles to avoid bus contention; although, if

the output bus has been activated by a low on E

and G,a lowon W will disable the outputs tWLQZ

after W falls.

Figure 9. WRITE Enable Controlled, WRITE AC Waveforms

Figure 10. Chip Enable Controlled, WRITE AC Waveforms

AI00926

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A14

DQ0-DQ7

VALID

tAVWH

tAVEL

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX

AI00927

tAVAV

tEHAX

tDVEH

A0-A14

DQ0-DQ7

VALID

tAVEH

tAVEL

tAVWL

tELEH

tEHDX

DATA INPUT

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