PAC5232 datasheet(39/66 Pages) ACTIVE-SEMI

39 / 66 page

Power Application Controller

-39-

Rev 1.1

6-Jan-2018

Figure 12-2 Typical Gate Driver Connections

PAC5232

DRBx

DRHx

DRSx

DRLx

VMOTOR

Table 12-1 Power Driver Resources by Part Numbers

PART

NUMBER

LOW-SIDE GATE DRIVER

HIGH-SIDE GATE DRIVER

DRLx

SOURCE/SINK CURRENT

DRHx

SOURCE/BOOTSTRAP

SUPPLY

SOURCE/SINK CURRENT

PAC5232

2A/2A

165V/180V

2A/2A

The ASPD includes built-in configurable fault protection for the internal gate drivers.

12.4

Low-Side Gate Driver

The DRLx low-side gate driver drives the gate of an external MOSFET or IGBT switch between the low-

level power ground rail and high-level VP supply rail. The DRLx output pin has sink and source output

current capability of 2A. Each low-side gate driver is controlled by a microcontroller port signal with 4

configurable levels of propagation delay.

12.5

High-Side Gate Driver

The DRHx high-side gate driver drives the gate of an external MOSFET or IGBT switch between its low-

level DRSx driver source rail and its high-level DRBx bootstrap rail. The DRSx pin can go up to 160V

steady state (VM + 15V maximum). The DRHx output pin has sink and source output current capability of

2A.

The DRBx bootstrap pin can have a maximum operating voltage of 15V relative to the DRSx pin, and up

to 175V steady state. The DRSx pin can have a maximum operating voltage of 10V relative to the VM pin.

The DRSx pin is designed to tolerate momentary switching negative spikes down to -10V without

affecting the DRHx output state. Each high-side gate driver is controlled by a microcontroller port signal

with 4 configurable levels of propagation delay.

For bootstrapped high-side operation, connect an appropriate capacitor between DRBx and DRSx and a

properly rated bootstrap diode from VP to DRBx. To operate the DRHx output as a low-side gate driver,

connect its DRBx pin to VP and its DRSx pin to VSS.

12.6

Power Drivers Control

All power drivers are initially disabled from power-on-reset. To enable the power drivers, the MCU must

first enable the ASPD block. The gate drivers are controlled by the microcontroller ports and/or PWM

PAC5232 Datasheet(PDF) 39 Page - Active-Semi, Inc

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