Rev 1.0

Page 3 of 12

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Table 4. Electrical Characteristics – HCSL

Parameter

Symbol

Min.

Typ.

Max.

Unit

Condition

Current Consumption

Current Consumption

Idd

–

–

89

mA

Excluding Load Termination Current, Vdd = 3.3V or 2.5V

OE Disable Supply Current

I_OE

–

–

58

mA

OE = Low

Output Disable Leakage Current

I_leak

–

0.15

–

µ

A

OE = Low

Maximum Output Current

I_driver

–

–

36

mA

Maximum average current drawn from OUT+ or OUT-

Output Characteristics

Output High Voltage

VOH

0.60

–

0.90

V

See Figure 2

Output Low Voltage

VOL

-0.05

–

0.08

V

See Figure 2

Output Differential Voltage Swing

V_Swing

1.2

1.4

1.8

V

See Figure 3

Rise/Fall Time

Tr, Tf

–

360

465

ps

Measured with 2 pF capacitive loading to GND, 20% to 80%,

see Figure 2

Jitter

RMS Phase Jitter (random)

T_phj

–

0.220

0.270

ps

f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Includes

spurs. Vdds, 7.0 x 5.0 mm package.

–

0.230

0.275

ps

f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Includes

spurs. Vdds, 7.0 x 5.0 mm package. 3.2 x 2.5 package = 0.275 ps.

–

0.1

–

ps

f = 156.25, IEEE802.3-2005 10GbE jitter mask integration bandwidth =

1.875 MHz to 20 MHz, Includes spurs, all Vdds

RMS Period Jitter

[3]

T_jitt

–

1.0

1.6

ps

f = 100, 156.25 or 212.5 MHz, VDD = 3.3V or 2.5V

Notes:

3. Measured according to JESD65B

Table 5. Pin Description

Pin

Map

Functionality

1

OE/NC

Output Enable

(OE)

H

[4]

: specified frequency output

L: output is high impedance

Non Connect

(NC)

H or L or Open: No effect on output frequency or other device

functions

2

NC

NA

No Connect; Leave it floating or connect to GND for better heat

dissipation

3

GND

Power

VDD Power Supply Ground

4

OUT+

Output

Oscillator output

5

OUT-

Output

Complementary oscillator output

6

VDD

Power

Power supply voltage

[5]

Notes:

4. In OE mode, a pull-up resistor of 10 kΩ or less is recommended if pin 1 is not externally driven.

5. A capacitor of value 0.1 µF or higher between Vdd and GND is required. An additional 10 µF capacitor

between Vdd and GND is required for the best phase jitter performance

Top View

Figure 1. Pin Assignments