MP8758H–22V, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER

MP8758H Rev.1.0

www.MonolithicPower.com

13

10/13/2015

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At a light-load or no-load condition, the output

drops very slowly until the MP8758H reduces the

switching frequency, achieving high efficiency at

light load.

Figure 3: Light-Load Operation

As the output current increases from the light-

load condition, the time period within the current

modulator becomes shorter. The HS-FET turns

on more frequently and the switching frequency

increases. The output current reaches critical

levels when the current modulator time is zero.

The critical level of the output current is

determined by Equation (1):

IN

OUT

OUT

OUT

SIN

(V

V

) V

I

2L F

V

−×

=

××

×

(1)

PWM mode begins once the output current

exceeds

the

critical

level.

The

switching

frequency then stays fairly constant over the

output current range.

Jitter and FB Ramp Slope

Jitter occurs in both PWM and skip mode when

HS-FET driver (see Figure 4 and Figure 5). Jitter

can affect system stability, with noise immunity

affect noise immunity.

V

RE F

V

FB

HS D river

J itter

V

S L O PE1

Figure 4: Jitter in PWM Mode

V

FB

HS D river

Jitter

V

REF

V

SL O P E 2

Figure 5: Jitter in Skip Mode

Operating

without

External

Ramp

Compensation

The traditional constant-on-time control scheme

is intrinsically unstable if the output capacitor’s

ESR is not large enough to act as an effective

current

sense

resistor.

Usually,

ceramic

capacitors cannot be used as output capacitors.

To determine the stability, calculate the ESR

value with Equation (2):

SW

ON

ESR

OUT

TT

0.7

2

R

C

+

×π

≥

(2)

The MP8758H has a built-in internal ramp

compensator to ensure that the system is stable,

even without the help of the output capacitor’s

ESR. Use a ceramic capacitor to significantly

reduce the output ripple, total BOM cost, and

board area.

Figure 6 shows a typical output circuit in PWM

mode without an external ramp circuit. Please

refer to the Application Information section on

page 17 for design steps without external

compensation.

R1

R2

CAP

SW

FB

Vo

L

C4

Figure 6: Simplified Circuit in PWM Mode without

External Ramp Compensation

When using a large ESR capacitor on the output,

add a ceramic capacitor with a value of 10µF or

less in parallel to minimize the effect of the ESL.