| Electronic Components Datasheet Search |
|
MP024-10 Datasheet(PDF) 21 Page - Monolithic Power Systems |
|
|
|||||||||||||||||||||||||||||
MP024-10 Datasheet(HTML) 21 Page - Monolithic Power Systems |
|
21 / 25 page ![]() MP024-10 – PRIMARY-SIDE CC/CV REGULATOR MP024-10 Rev.1.0 www.MonolithicPower.com 21 4/17/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. Maximum Switching Frequency The maximum switching frequency should be limited by the sampling point. The relationship between RSS and the sampling time point is shown in the Electrical Characteristics table on page 5. The secondary on time must be longer than the maximum TFBS-Max. Calculate TS_ON with Equation (15): SM S _ ON PK FBS _ Max FB _ SD P O D NL T I t t N (V V ) (15) Where TFBS-Max is the FB maximum sampling time, and tFB_SD is the FB sampling duration. Combine Equation (14) and the relationship of RCP and DS-Max shown in Table 1 to fix the maximum switching frequency. PCB Layout Guidelines Efficient PCB layout is critical for stable operation, good EMI, and good thermal performance. For best results, refer to Figure 15 and follow the guidelines below. 1. Minimize the loop area formed by the input capacitor, the transformer ’s primary winding, the MOSFET drain and source of the MP024-10, and the sensing resistor to reduce EMI noise. 2. Minimize the voltage jumping area, such as the MOSFET drain, the anode of the secondary diode, etc. for better EMI. 3. Minimize the clamp circuit loop to reduce EMI. 4. Minimize the secondary loop area of the output diode and output filter to reduce EMI noise. 5. Provide sufficient copper areas at the cathode terminal of the output diode to act as a heat sink. 6. Place the AC input away from the switching nodes to minimize any noise coupling that may bypass the input filter. 7. Place the bypass capacitor as close to the IC as possible. 8. Place the feedback resistors next to FB and minimize the feedback sampling loop to minimize noise coupling. 9. Use a single-point connection at the negative terminal of the input filter capacitor for the IC GND and bias winding return. Top Layer Bottom Layer Figure 15: Recommended Layout Design Example Table 2 shows a design example following the application guidelines. Table 2: Design Example VIN 85Vac~265Vac, 47Hz/63Hz VOUT 5V IOUT 2A Figure 16 shows the detailed application schematic. For more device applications, please refer to the related evaluation board datasheets. |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |