LTC2992 datasheet(21/46 Pages) LINER

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LTC2992

Rev A

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APPLICATIONS INFORMATION

condition by transitioning SDA from low to high while SCL

stays high. The bus is then free for another transmission.

Stuck-Bus Reset

TheLTC2992I2Cinterfacefeaturesastuck-busresettimer

to prevent it from holding the bus lines low indefinitely if

the SCL signal is interrupted during a transfer. The timer

starts when either SCL or SDAI is low, and resets when

both SCL and SDAI are pulled high. If either SCL or SDAI

are low for over 33ms, the stuck-bus timer will expire, and

the internal I2C interface and the SDAO pin pull-down logic

will be reset to release the bus. Normal communication

will resume at the next START command.

Acknowledge

The acknowledge signal is used for handshaking between

the master and the slave to indicate that the last byte of

data was received. The master always releases the SDA

line during the acknowledge clock pulse. The LTC2992 will

pull the SDA line low on the 9th clock cycle to acknowledge

receipt of the data. If the slave fails to acknowledge by

leaving SDA high, then the master can abort the transmis-

sion by generating a STOP condition. When the master is

receivingdatafromtheslave,themastermustacknowledge

the slave by pulling down the SDA line during the 9th clock

pulse to indicate receipt of a data byte. After the last byte

has been received by the master, it will leave the SDA line

high (not acknowledge) and issue a STOP condition to

terminate the transmission.

Write Protocol

The master begins a write operation with a START condi-

tion followed by the 7-bit slave address and the R/W bit

set to zero. After the addressed LTC2992 acknowledges

the address byte, the master then sends a command byte

that indicates which internal register the master wishes to

write. The LTC2992 acknowledges this and then latches

thecommandbyteintoitsinternalregisteraddresspointer.

The master then delivers the data byte and the LTC2992

acknowledges once more and writes the data into the in-

ternal register pointed to by the register address pointer. If

the master continues sending additional data bytes with a

writewordorextendedwritecommand,theadditionaldata

bytes will be acknowledged by the LTC2992, the register

address pointer will automatically increment by one, and

data will be written as previously stated. The write opera-

tion terminates and the register address pointer resets to

0x00 when the master sends a STOP condition.

Read Protocol

The master begins a read operation with a START condi-

tion followed by the 7-bit slave address and the R/W bit

set to zero. After the addressed LTC2992 acknowledges

the address byte, the master then sends a command byte

that indicates which internal register the master wishes to

read.TheLTC2992acknowledgesthisandthenlatchesthe

command byte into its internal register address pointer.

The master then sends a repeated START condition fol-

lowed by the same 7-bit address with the R/W bit now set

to 1. The LTC2992 acknowledges and sends the contents

of the requested register. The transmission terminates

when the master sends a STOP condition. If the master

acknowledges the transmitted data byte, as in a read word

command, the LTC2992 will send the contents of the next

will keep incrementing the register address pointer and

sending out data bytes. The read operation terminates

and the register address pointer resets to 0x00 when the

master sends a STOP condition.

Alert Response Protocol

When any of the fault bits in the fault registers (FAULT1,

FAULT2, FAULT3 and FAULT4) are set, a bus alert is gener-

ated if the appropriate bit in the ALERT1, ALERT2, ALERT3

or ALERT4 registers has been set. This allows the bus

mastertoselectwhichfaultswillgeneratealerts.Atpower-

up, all ALERT registers are cleared (no alerts enabled) and

the GPIO4 (ALERT) pin is high. If an alert is enabled, the

corresponding fault causes the GPIO4 (ALERT) pin to pull

low. The bus master responds to the alert in accordance

with the SMBus alert response protocol by broadcasting

the alert response address (0001100)b, and the LTC2992

replieswithitsownaddressandreleasesitsGPIO4(ALERT)

pin, as shown in Figure 15. The GPIO4 (ALERT) line is also

released if CTRLB[7] is set and the LTC2992 is addressed

(see Table 6) by any message. The GPIO4 (ALERT) signal

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