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LTC3351

3351f

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OPERATION

capacitance and ESR measurement system may tempo-

rarily increase this DAC to a value as much as full scale

(1.2V) during the ESR test.

If using the capacitance and ESR test, the highest usable

DAC setting will be determined by the voltage increase

between that setting and 1.2V at the CAPFB pin, wherein

the capacitor stack’s voltage increases by 1.25 times the

voltage specified in cap_delta_v_setting.

Charge Status Indication

The LTC3351 includes a comparator to report the status

of the supercapacitors via an open-drain NMOS transis-

tor on the CAPGD pin. This pin pulls to ground until the

CAPFBpinvoltagerisestowithinnominally8%oftheVCAP

DAC setting. Once the CAPFB pin is above this threshold,

the CAPGD pin goes high impedance. The output of this

comparator may also be read from the cappg bit in the

sys_status register.

Capacitor Voltage Balancer

The LTC3351 has an integrated active stack balancer. This

balancer slowly balances all of the capacitor voltages to

within approximately 10mV of each other. This maximizes

the life of the supercapacitors by keeping the voltage on

each as low as possible to achieve the needed total stack

voltage. When the difference between any two capacitor

voltages exceeds approximately 10mV, the capacitor with

the largest voltage is discharged with a resistive balancer

(approximately 75Ω until all capacitor voltages are within

10mV). The balancers can be disabled by setting the

ctl_disable_balancer bit.

Capacitor Shunt Regulators

During charging, the capacitors are protected from over-

voltage. The capacitors in the stack will not have exactly

the same capacitance due to manufacturing tolerances

or uneven aging. This will cause the capacitor voltages to

increase at different rates with the same charge current.

If this mismatch is severe enough or if the capacitors are

being charged to near their maximum voltage, it becomes

necessary to limit the voltage increase on some capacitors

while still charging the other capacitors. Up to 500mA of

current may be shunted around a capacitor whose voltage

is approaching the programmable shunt voltage. This

shunt current reduces the charge rate of that capacitor

relative to the other capacitors. If a capacitor continues

to approach its shunt voltage, the stack charge current is

reduced.Thisprotectsthecapacitorfromovervoltagewhile

still charging the other capacitors, although at a reduced

rate of charge. When shunting, the internal switch may

be on more than 96% duty cycle. The shunts are disabled

by setting the ctl_disable_shunt bit. The shunt voltage

is programmable in the vshunt register. Shunt voltages

may be programmed in 183.5µV increments. If a voltage

greater than 3.6V is programmed, the charge current will

be reduced as that voltage is approached but the shunt

will not turn on. The default value is 0x3999, resulting in

a shunt voltage of approximately 2.7V. See Register Map

for more information.

I2C/SMBus and SMBALERT

The LTC3351 contains an I2C/SMBus compatible port.

This port allows communication with the LTC3351 for

configuration and reading back telemetry data. The port

supports two SMBus formats, read word and write word.

These may be used with or without the packet error code

(PEC) feature. Refer to the SMBus specification for de-

tails of these formats and PEC. The registers accessible

via this port are organized on an 8-bit address bus and

each register is 16 bits wide. The “command code” (or

sub-address) of the SMBus read/write word formats is

the 8-bit address of each of these registers. The address

of the LTC3351 is 0b0001001.

The SMBALERT pin is asserted (pulled low) whenever

an enabled limit is exceeded or when an enabled status

event happens (see the Limit Checking and Alarms and

the Monitor Status Register sections of this data sheet).

The LTC3351 will de-assert the SMBALERT pin only after

responding to a SMBus alert response address (ARA),

an SMBus protocol used to respond to a SMBALERT.

The host will read from the ARA (0b0001100) and each

part asserting SMBALERT will begin to respond with its

address. The responding parts arbitrate in such a way that

onlythepartwiththelowestaddressrespondscompletely.

Only when a part has responded with its entire address

does it release the SMBALERT signal. If multiple parts

are asserting the SMBALERT signal then multiple reads

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