DAC5674

SLWS148 − SEPTEMBER 2003

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21

PFD

ref

ICO

Fref

Fvco

LPF

R

C1

C2

DAC5674

External Loop Filter

PN

Figure 22. PLL Functional Block Diagram

Table 5. DAC5674 Evaluation Board PLL Loop Filter Parameters

N(1)

PHASE MARGIN (DEGREES)

BANDWIDTH (MHZ)

2

60

1.6

4

71

1.4

8

77

1

16

78

0.7

32

74

0.4

(1) N is the VCO divide-down factor from prescale and interpolation.

Digital Inputs

Figure 23 shows a schematic of the equivalent CMOS digital inputs of the DAC5674. The CMOS-compatible

inputs have logic thresholds of IOVDD/2

±20%. The 14-bit digital data input follows the offset positive binary

coding scheme.

D[13:0]

SLEEP

EXTLO

DIV[1:0]

RESET

HP1, HP2

Internal

Digital In

IOVDD (AVDD for SLEEP and EXTLO)

IOGND

Figure 23. CMOS/TTL Digital Equivalent Input

Clock Input and Timing

Figure 24 shows the clock and data input timing diagram for internal and external clock modes, respectively.

Note that a negative value indicates a reversal of the edge positions as shown in the timing diagram. Figure 24