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LTM2892

2892fa

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Inter-IC Communication (I2C) Bus

The LTM2892-I provides an isolated I2C compatible inter-

face supporting master mode only, with a unidirectional

clock (SCLIN), and bidirectional data (SDA1). The maxi-

mum data rate is 400kHz which supports fast-mode I2C.

Timing is detailed in Figure 10. The data rate is limited by

the slave acknowledge setup time (tSU;ACK), consisting of

the I2C standard minimum setup time (tSU;DAT) of 100ns,

maximumclockpropagationdelayof225ns,glitchfilterand

isolated data delay of 500ns maximum, and the combined

isolated and logic data fall time of 300ns at maximum bus

loading.ThetotalsetuptimereducestheI2Cdataholdtime

(tHD;DAT) to a maximum of 175ns, guaranteeing sufficient

data setup time (tSU;ACK).

applicaTions inForMaTion

The isolated side bidirectional serial data pin, SDA2,

simplified schematic is shown in Figure 11. An internal

1.8mA current source provides a pull-up for SDA2. Do not

connect any other pull-up device to SDA2. This current

source is sufficient to satisfy the system requirements

for bus capacitances greater than 200pF in fast mode and

greater than 400pF in standard mode.

Additional proprietary circuitry monitors the slew rate on

the SDA1 and SDA2 signals to manage directional control

across the isolation barrier. Slew rates on both pins must

be greater than 1V/μs for proper operation.

Figure 10. I2C Timing Diagram

Figure 11. Isolated SDA2 Pin Schematic

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SDA2

1.8mA

GLITCH

FILTER

TO LOGIC SIDE

FROM LOGIC SIDE

2892 F10

tPROP

tSU;DAT

SDA1

SDA2

SCLIN

SCLOUT

tHD;DAT

tSU;ACK

STOP

START

SLAVE ACK

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