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LTC3676/LTC3676-1

3676ff

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THERMAL CONSIDERATIONS AND BOARD LAYOUT

Printed Circuit Board Power Dissipation

In order to ensure optimal performance and the ability

to deliver maximum output power to any regulator, it is

critical that the exposed ground pad on the backside of the

LTC3676 package be soldered to a ground plane on the

board. The exposed pad is the only GND connection for the

LTC3676. Correctly soldered to a 2500mm2 ground plane

on a double-sided 1oz copper board, the LTC3676 has a

thermalresistance(

JA)ofapproximately34°C/W.Failure

to make good thermal contact between the exposed pad

on the backside of the package and an adequately sized

ground plane will result in thermal resistances far greater

than 34°C/W. To ensure the junction temperature of the

LTC3676 die does not exceed the maximum rated limit

and to prevent overtemperature faults, the power output

of the LTC3676 must be managed by the application. The

total power dissipation in the LTC3676 is approximated by

summing the power dissipation in each of the switching

regulators and the LDO regulators. The power dissipation

in a switching regulator is estimated by:

PD SWx

(

) = VOUTx •IOUTx •

100-Eff%

100

( )

Where VOUTx is the programmed output voltage IOUTx is

the load current and Eff is the % efficiency that can be

measured or looked up from the efficiency curves for the

programmed output voltage.

The power dissipated by an LDO regulator is estimated by:

PD(LDOx) = VIN(LDOx) − VLDOx • ILDOx (W)

where VLDOx is the programmed output voltage, VIN(LDOx)

is the LDO supply voltage, and ILDOx is the output load

current. If one of the switching regulator outputs is used

as an LDO supply voltage, remember to include the LDO

supply current in the switching regulator load current for

calculating power loss.

An example using the equations above with the param-

eters in Table 23 shows an application that is at a junction

temperature of 120°C at an ambient temperature of 55°C.

LDO2, LDO3, and LDO4 are powered by step-down Buck2

and Buck4. The total load on Buck2 and Buck4 is the sum

of the application load and the LDO load. This example

is with the LDO regulators at one third rated current and

the switching regulators at three quarters rated current.

Table 23. LTC3676 Power Loss Example

VIN

VOUT

APPLICATION

LOAD (A)

TOTAL

LOAD (A)

EFF

(%) PD (mW)

LDO1

3.8

1.2

0.01

0.010

–

26.00

LDO2

1.8

1.2

0.1

0.100

–

60.00

LDO3

3.3

1.8

0.1

0.100

–

150.00

LDO4

3.3

2.5

0.1

0.100

–

80.00

Buck1

3.8

1.2

1.875

450.00

Buck2

3.8

1.8

1.775

1.875

506.25

Buck3

3.8

1.25

1.125

281.25

Buck4

3.8

3.3

0.925

1.125

371.25

Total Power =

1925

Internal Junction Temperature at 55°C Ambient

120°C

Printed Circuit Board Layout

When laying out the printed circuit board, the following

checklist should be followed to ensure proper operation

of the LTC3676:

1. Connect the exposed pad of the package (Pin 41) di-

rectly to a large ground plane to minimize thermal and

electrical impedance.

2. The switching regulator input supply traces to their

decoupling capacitors should be as short as possible.

Connect the GND side of the capacitors directly to the

ground plane of the board. The decoupling capacitors

provide the AC current to the internal power MOSFETs

and their drivers. It is important to minimize inductance

from the capacitors to the LTC3676 pins.

3. Minimize the switching power traces connecting SW1,

SW2, SW3, and SW4 to the inductors to reduce radi-

ated EMI and parasitic coupling. Keep sensitive nodes

such as the feedback pins away from or shielded from

the large voltage swings on the switching nodes.

4. Minimize the length of the connection between the

step-downswitchingregulatorinductorsandtheoutput

capacitors. Connect the GND side of the output capaci-

tors directly to the thermal ground plane of the board.

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