HIP1011D, HIP1011E

FN4725 Rev 5.00

Page 11 of 15

November 18, 2004

Using the HIP1011DEVAL1 Platform

General and Biasing Information

The HIP1011DEVAL1 platform (Figure 24) comes as a three

part set consisting of 1 motherboard emulator and 2 load

cards. This evaluation platform allows a designer to evaluate

and modify the performance and functionality of the

HIP1011D or HIP1011E in a simple environment.

Test point numbers (TP#) correspond to the HIP1011D/E

device (U5) pin numbers. Thus TP3 and TP12 are

PWRON_2 and PWRON_1 respectively. These 2 pins are

the HIP1011D/E control inputs for each of the 2 integrated

but independent PCI power controllers in the HIP1011D/E.

On the HIP1011DEVAL1 platform are 4 HUF76132SK8,

(11.5m

, 30V, 11.5A) N-Channel power MOSFETs, (Q1- Q4)

these are used as the external switches for the +5V and

+3.3V supplies to the load card connectors, P1 and P2.

Current sensing is facilitated by the four 5m

 1W metal strip

resistors (R1-R4), the voltages developed across the sense

resistors are compared to references on board the

HIP1011D/E.

The HIP1011DEVAL1 platform is powered through the J1 to

J5 connector jacks near the top of the board (see Table 2 for

bias voltage assignments.)

After properly biasing the HIP1011D/E and ensuring there is an

adequate ground return from the HIP1011DEVAL1 platform to

the power supplies, (otherwise anomalous and unpredictable

results will occur) signal the PWRON inputs low then insert the

load cards as shown in Figure 15. Signaling either or both

PWRON pins high (>2.4V) will turn on the appropriate FET

switches and apply voltage to the load cards.

* The HIP1011DEVAL board is supplied with a HIP1011D

installed and in addition a loose packed HIP1011E.

Evaluating Time Delay to Latch-Off

Provided for delay to latch-off evaluation are 2 locations for

SMD capacitors, C7 and C8. Filling these locations places a

capacitor to ground from each of the HIP1011D/E FLTN pins

thus tailoring the FLTN signal going low ramp rate. This

provides a delay to the fault signal latch-off threshold

voltage, FLTN Vth. By increasing this time the HIP1011D

delays immediate latch-off of the bus supply switches, thus

ignoring transient OC and UV conditions. See Table 3

illustrating the time it takes for switch gate turn-off from the

FLTN start of response to an OC or UV condition. The FLTN

response to an OC or UV condition is 110ns. See Figures 20

through 23 for waveforms.

The intent of any protection device is to isolate the supply

quickly so a faulty card does not drag down a supply. A

longer latch-off delay results in less isolation from a faulty

card to supply.

TABLE 2. HIP1011DEVAL1 BIAS ASSIGNMENTS

J1

J2

J3

J4

J5

GND

+5V

-12V

+12V

+3.3V

LOAD CARDS

HIP1011D

FIGURE 15. CORRECT INSTALLATION OF LOAD CARDS

TABLE 3.

C7 AND C8 VALUE

OPEN

0.001

F0.01F0.1F

FLTN to Gate Response

0.1

s0.44s2.9s28s

3V5VG

FLTN

FLTN, Vth

FIGURE 16. TIMING DIAGRAM

1ns

10ns

100ns

1µs

10µs

100µs

1ms

10ms

0.001µF

0.1µF

1µF

10µF

OPEN

0.01µF

FIGURE 17. TYPICAL OC/UV TO VG RESPONSE vs FLTN CAP