ISL6232 datasheet(21/25 Pages) RENESAS

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ISL6232

FN9116 Rev 1.00

Page 21 of 25

April 20, 2009

Input Capacitor Selection

The input capacitors must meet the input ripple current

(IRMS) requirement imposed by the switching current. The

ISL6232 dual switching regulators operate at the same

switching frequency with out-of-phase. This interleaves the

current pulses drawn by the two regulators and have no

overlap time at normal operation. The input RMS current is

much smaller when compared with both regulators operating

in phase or operating at different switching frequencies. The

input RMS current varies with load and the input voltage.

The maximum input capacitor RMS current for a single buck

regulator is given by Equation 16:

when VIN = 2VOUT (D = 50%), IRMS has maximum current

of IOUT/2. The ESR of the input capacitor is important for

determining capacitor power dissipation. All the power

(I2RMS x ESR) heats up the capacitor and reduces

efficiency. Non-tantalum chemistries (ceramic, polymer such

as POSCAP, or SPCAP) are preferred due to their low ESR

and resilience to power-up surge currents. Choose input

capacitors that exhibit less than +10°C temperature rise at

the RMS input current for optimal circuit longevity.

MOSFET Selection

The synchronous buck regulator has the input voltage from

either AC-adapter output or battery output. The maximum

AC-adapter output voltage does not exceed 24V while the

maximum battery voltage does not exceed 17V for a 4 series

Li-ion battery cell battery pack. Therefore, a 30V logic

MOSFET should be used.

The high side MOSFET must be able to dissipate the

conduction losses plus the switching losses. The input

voltage of the synchronous regulator is equal to the

AC-adapter output voltage or battery voltage. The maximum

efficiency is achieved by selecting a high side MOSFET that

has the conduction losses equal to the switching losses.

Ensure that the ISL6232 LGATE gate driver can supply

sufficient gate current to prevent it from conduction,

otherwise, cross-conduction problems may occur.

Conduction is due to the injected current into the

drain-to-gate parasitic capacitor (Miller capacitor Cgd)

caused by the voltage rising rate at phase node during the

moment of the high-side MOSFET turn-on. Reasonably

slowing turn-on speed of the high-side MOSFET by

connecting a resistor between the BOOT pin and gate drive

supply source, and high sink current capability of the

low-side MOSFET gate driver, helps reduce the possibility of

cross-conduction.

For the high-side MOSFET, the worst-case conduction

losses occur at the minimum input voltage as shown in

Equation 17:

The optimum efficiency occurs when the switching losses

equal the conduction losses. However, it is difficult to

calculate the switching losses in the high-side MOSFET

since it must allow for difficult-to-quantify factors that

influence the turn-on and turn-off times. These factors

include the MOSFET internal gate resistance, gate charge,

threshold voltage, stray inductance, and the pull-up and

pull-down resistance of the gate driver. The following

switching loss calculation (Equation 18) provides a rough

estimate.

where Qgd: drain-to-gate charge, Qrr: total reverse recovery

charge of the body-diode in low side MOSFET, ILV: inductor

valley current, ILP:is Inductor peak current, Ig,sink and

Ig,source are the peak gate-drive source/sink current of Q1.

To achieve low switching losses requires low drain-to-gate

charge Qgd. Generally, the lower the drain-to-gate charge,

the higher the ON-resistance. Therefore, there is a trade-off

between the ON-resistance and drain-to-gate charge. Good

MOSFET selection is based on the Figure of Merit (FOM),

which is the product of the total gate charge and

ON-resistance. Usually, the smaller the value of FOM, the

higher the efficiency for the same application.

For the low-side MOSFET, the worst-case power dissipation

occurs at minimum output voltage and maximum input

voltage:

Choose a low-side MOSFET that has the lowest possible

ON-resistance with a moderate-sized package, like SO-8,

and one that is reasonably priced. The switching losses are

not an issue for the low side MOSFET because it operates at

zero-voltage-switching.

Choose an Schottky diode, in parallel with the low side

MOSFET Q2, with a forward voltage drop low enough to

prevent the low-side MOSFET Q2 body-diode from turning

on during the dead time. This also reduces the power loss in

the high-side MOSFET associated with the reverse recovery

of the low-side MOSFET Q2 body diode. As a general rule,

select a diode with a DC current rating equal to one-third of

the load current. One option is to choose a combined

MOSFET with the Schottky diode in a single package. The

integrated packages may work better in practice because

there is less stray inductance due to short connection. This

Schottky diode is optional and may be removed if efficiency

loss can be tolerated.

Irms IOUT

VOUT VIN VOUT

–



VIN

---------------------------------------------------------

(EQ. 16)

PQ1 Conduction



VOUT

VIN

----------------IOUT

rDS ON



(EQ. 17)

PQ1 Switching



---VINILVfs

Qgd

Igsource



------------------------- 1

---VINILPfs

Qgd

Igk

sin



----------------- QrrVINfs

(EQ. 18)

PQ2

VOUT

VIN

----------------

–







IOUT

rDS ON



(EQ. 19)

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