 2000 Microchip Technology Inc.

DS39504A-page 4-5

Section 4 Architecture

4

4.2

Clocking Scheme/Instruction Cycle

The clock input is internally divided by four to generate four non-overlapping quadrature clocks,

namely Q1, Q2, Q3 and Q4. Internally, the program counter is incremented every Q1, and the

instruction is fetched from the program memory and latched into the instruction register in Q4.

The instruction is decoded and executed during the following Q1 through Q4. The clocks and

instruction execution flow are illustrated in Figure 4-3 and Example 4-1.

Figure 4-3: Clock/Instruction Cycle

4.2.1

Phase Lock Loop (PLL)

The clock input is multiplied by four by the PLL. Therefore, when it is internally divided by four, it

provides an instruction cycle that is the same frequency as the external clock frequency. Four

non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4 are still generated internally.

Internally, the program counter (PC) is incremented every Q1, and the instruction is fetched from

the program memory and latched into the instruction register in Q4. The instruction is decoded

and executed during the following Q1 through Q4. The clocks and instruction execution flow are

illustrated in Figure 4-4 and Example 4-1.

Figure 4-4: Clock/Instruction Cycle with PLL

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Device Clock

Q1

Q2

Q3

Q4

PC

CLKOUT

(RC mode)

PC

PC+2

PC+4

Fetch INST (PC)

Execute INST (PC-2)

Fetch INST (PC+2)

Execute INST (PC)

Fetch INST (PC+4)

Execute INST (PC+2)

Internal

phase

clock

(OSC1 or T1OSCI)

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

PLL Output

Q1

Q2

Q3

Q4

PC

OSC2/CLKOUT

(RC mode)

PC

PC+2

PC+4

Fetch INST (PC)

Execute INST (PC-2)

Fetch INST (PC+2)

Execute INST (PC)

Fetch INST (PC+4)

Execute INST (PC+2)

Internal

phase

clock