DLPC3432CZVB datasheet(7/60 Pages) TI1

7 / 60 page

DLPC3432

www.ti.com

DLPS108B – FEBRUARY 2018 – REVISED APRIL 2018

Product Folder Links: DLPC3432

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(1)

For DSI, differential data bus(0) is required for DSI operation with the remaining 3 data lanes being optional or implementation specific

as needed. Any unused DSI LVDS pairs should be unconnected and left floating.

(2)

RREF is an analog signal that requires a fixed precision resistor connected to this pin when DSI is utilized. If DSI is NOT utilized then this

signal should be unconnected and left floating on the board design.

Pin Functions - DSI Input Data and Clock

Added PIN

I/O

DESCRIPTION

NAME

NUMBER

MIPI DSI MODE

DCLKN

DCLKP

B10

DSI interface; DSI - LVDS differential clock

DD0N

DD0P

DD1N

DD1P

DD2N

DD2P

DD3N

DD3P

B10

DSI interface, DSI data lane LVDS differential pair inputs 0 to 3

(Support a maximum of 4 input DSI lanes)(1)

RREF

DSI reference resistor: A 30 kΩ ± 1% external trim resistor should

be connected from this pin to ground(2)

Pin Functions – DMD Reset and Bias Control

I/O

DESCRIPTION

NAME

NUMBER

DMD_DEN_ARSTZ

DMD driver enable (active high) or DMD reset (active low). Assuming the

corresponding I/O power is supplied, this signal will be driven low after the DMD is

parked and before power is removed from the DMD. If the 1.8-V power to the

DLPC3432 is independent of the 1.8-V power to the DMD, then TI recommends a

weak, external pulldown resistor to hold the signal low in the event the DLPC3432

power is inactive while DMD power is applied.

DMD_LS_CLK

DMD, low speed interface clock

DMD_LS_WDATA

DMD, low speed serial write data

DMD_LS_RDATA

DMD, low speed serial read data

Pin Functions – DMD Sub-LVDS Interface

I/O

DESCRIPTION

NAME

NUMBER

DMD_HS_CLK_P

DMD_HS_CLK_N

DMD high speed interface

DMD_HS_WDATA_H_P

DMD_HS_WDATA_H_N

DMD_HS_WDATA_G_P

DMD_HS_WDATA_G_N

DMD_HS_WDATA_F_P

DMD_HS_WDATA_F_N

DMD_HS_WDATA_E_P

DMD_HS_WDATA_E_N

DMD_HS_WDATA_D_P

DMD_HS_WDATA_D_N

DMD_HS_WDATA_C_P

DMD_HS_WDATA_C_N

DMD_HS_WDATA_B_P

DMD_HS_WDATA_B_N

DMD_HS_WDATA_A_P

DMD_HS_WDATA_A_N

A10

B10

A11

B11

DMD high speed interface lanes, write data bits: The true numbering and

application of the DMD_HS_DATA pins are software configuration dependent

DLPC3432CZVB Datasheet(PDF) 7 Page - Texas Instruments

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