ISL8200AMMRZ datasheet(13/25 Pages) RENESAS

13 / 25 page

ISL8200AM

FN8271 Rev.7.00

Page 13 of 25

Apr 27, 2018

Applications Information

Programming the Output Voltage (RSET)

The ISL8200AM has an internal 0.6V ±0.7% reference voltage.

Programming the output voltage requires a dividing resistor

(RSET) between the VOUT_SET pin and the VOUT regulation point.

The output voltage can be calculated as shown in Equation 1:

Note: The ISL8200AM has integrated 2.2kΩ resistances into the

module dividing resistor for the bottom side (ROS). The

resistances for different output voltages in single-phase

operation are listed in Table 1.

The output voltage accuracy can be improved by maintaining the

impedance at VOUTSET (internal VSEN1+) at or below 1kΩ

effective impedance. Note: The impedance between VSEN1+ and

VSEN1- is about 500kΩ.

The module has a minimum input voltage at a given output

voltage, which needs to be a minimum of 1.43 times the output

voltage if operating at fSW = 700kHz switching frequency. This is

due to the minimum PWM OFF time (tMIN-OFF).

The equations to determine the minimum PVIN to support the

required VOUT are given by Equations 2 and 3; it is recommended

to add 0.5V to the result to account for temperature variations.

tSW = switching period = 1/fSW

for the 700kHz switching frequency = 1428ns

For 3.3V input voltage operation, the VIN voltage is

recommended to be 5V for sufficient gate drive voltage. This can

be accomplished by using a voltage greater than or equal to 5V

on VIN, or directly connecting the 5V source to both VIN and PVCC.

VIN is the input to the internal LDO that powers the control

circuitry while PVCC is the output of the aforementioned LDO.

PVIN is the power input to the power stage. Figure 22 shows a

scenario in which the power stage is running at 3.3V and the

control circuitry is running at 5V; keep in mind that the PVCC pin

is also at 5V to ensure that the LDO is not functioning. Figure 23

shows a setup in which both the control circuitry and the power

stage is at a 5V rail. It is imperative to not cross 5.5V in this setup

as that is the voltage limit on the PVCC pin. Figure 24 is a more

general setup and can accommodate VIN ranges up to 20V; PVCC

is not tied to VIN and hence the control circuitry is powered by the

internal LDO.

The circuit shown in Figure 25 ensures proper start-up by

injecting current into the ISHARE line until all phases are ready to

start regulating.

TABLE 1. VOUT - RSET

VOUT (V)

0.6

0.8

1.0

1.2

RSET (Ω)

732

1.47k

2.2k

VOUT (V)

1.5

1.8

2.0

2.5

RSET (Ω)

3.32k

4.42k

5.11k

6.98k

VOUT (V)

3.3

5.0

6.0

RSET (Ω)

10k

16.2k

20k

VOUT

0.6

RSET

ROS

---------------









(EQ. 1)

PVIN_MIN

VOUT tSW



tSW tMIN_OFF

–

------------------------------------------

(EQ. 2)

PVIN_MIN

1.43 VOUT



(EQ. 3)

FIGURE 22. 3.3V OPERATION

VIN = 5.0V

VOUT

RSET



VOUT_SET

VSEN_REM-

PVIN

ISL8200AM

POWER MODULE

VIN

VOUT

ISHARE

PGND1

VEN

PVCC = 5.0V

10µF

PVIN = 3.3V

VIN = 5.0V

VOUT

RSET

10µF



VOUT_SET

VSEN_REM-

PVIN

ISL8200AM

POWER MODULE

VIN

VOUT

ISHARE

PGND1

VEN

PVCC = VIN

DO NOT CROSS 5.5V

FIGURE 23. 5V OPERATION

VIN = 5V-20V

VOUT

RSET

10µF

VOUT_SET

VSEN_REM-

PVIN

ISL8200AM

POWER MODULE

VIN

VOUT

ISHARE

PGND1

VEN

FIGURE 24. 5V TO 20V OPERATION

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