ISL8277M datasheet(21/57 Pages) RENESAS

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ISL8277M

FN8923 Rev.1.00

Page 21 of 57

Aug 17, 2017

temperature still exceeds the fault limit, the controller waits the

preset delay period and retries the temperature.

Digital-DC Bus

The Digital-DC Communications (DDC) bus is used to

communicate between Intersil digital power modules and digital

controllers. This dedicated bus provides the communication

channel between devices for features such as sequencing and

fault spreading. The DDC pin on all Digital-DC devices in an

application should be connected together. A pull-up resistor is

required on the DDC bus to ensure the rise time as shown in

Equation 1:

where RPU is the DDC bus pull-up resistance and CLOAD is the

bus loading. The pull-up resistor may be tied to an external 3.3V

or 5V supply as long as this voltage is present before or during

device power-up. In principle, each device connected to the DDC

bus presents approximately 10pF of capacitive loading, and each

inch of FR4 PCB trace introduces approximately 2pF. The ideal

design uses a central pull-up resistor that is well-matched to the

total load capacitance.

Phase Spreading

When multiple point-of-load converters share a common DC

input supply, it is desirable to adjust the clock phase offset of

each device, such that not all devices start to switch

simultaneously. Setting each converter to start its switching cycle

at a different point in time can dramatically reduce input

capacitance requirements and efficiency losses. Because the

peak current drawn from the input supply is effectively spread

out over a period of time, the peak current drawn at any given

moment is reduced, and the power losses proportional to the

IRMS2 are reduced dramatically.

To enable phase spreading, all converters must be synchronized

to the same switching clock. The phase offset of each device

may also be set to any value between 0° and 360° in 22.5°

increments with PMBus command INTERLEAVE.

Output Sequencing

A group of Digital-DC modules or devices may be configured to

power-up in a predetermined sequence. This feature is especially

useful for preventing latch-up when powering advanced

processors (FPGAs and ASICs that require one supply to reach its

operating voltage) prior to another supply reaching its operating

voltage. Multi-device sequencing can be achieved by configuring

each device with PMBus command SEQUENCE. Multiple device

sequencing is configured by issuing PMBus commands to assign

the preceding device in the sequencing chain as well as the

device that follows in the sequencing chain.

The Enable pins of all devices in a sequencing group must be tied

together and driven high to initiate a sequenced turn-on of the

group. Enable must be driven low to initiate a sequenced turnoff

of the group.

Fault Spreading

Digital DC modules and devices can be configured to broadcast a

fault event over the DDC bus to the other devices in the group

with PMBus command DDC_GROUP. When a non-destructive

fault occurs and the device is configured to shutdown on a fault,

the device shuts down and broadcasts the fault event over the

DDC bus. The other devices on the DDC bus shutdown

simultaneously, if configured to do so, and attempt to restart in

their prescribed order.

Monitoring Via SMBus

A system controller can monitor a wide variety of different

ISL8277M system parameters with PMBus commands:

•READ_VIN

•READ_VOUT

•READ_IOUT

• READ_INTERNAL_TEMP

• READ_EXTERNAL_TEMP

• READ_DUTY_CYCLE

• READ_FREQEUNCY

•MFR_READ_VMON

Snapshot Parameter Capture

The ISL8277M offers a special feature to capture parametric data

and some fault status following a fault. A detailed description is

provided in “SNAPSHOT (EAh)” on page 48.

Nonvolatile Memory

The ISL8277M has internal nonvolatile memory that stores user

configurations. Integrated security measures ensure that users

can only restore the module to a level that has been made

available to them. During the initialization process, the ISL8277M

checks for stored values contained in its internal nonvolatile

memory.

Modules are shipped with factory default configurations. Most

settings can be overwritten with PMBus commands and can be

stored in nonvolatile memory with the PMBus command

STORE_USER_ALL.

PCB Layout Guidelines

To achieve stable operation, low losses, and good thermal

performance, some layout considerations are necessary.

•For VDD > 6V, the recommended PCB layout is shown in

Figure 29. Leave V25, VDDC, VR5, and VR6 as “No Connect

(NC)”.

• For 5.5V

 VDD  6V, connect VDDC pin to VR6 pin. For

4.5

 VDD < 5.5V, connect VDDC pin to VR6 and VR5 pin. An RC

filter is required at the input of VDRVIN pin if input supply is

shared with the VIN pin.

• Establish a separate SGND plane and PGND plane, then

connect the SGND to the PGND plane as shown in Figure 30 in

the middle layer. For making connections between

SGND/PGND on the top layer and other layers, use multiple

Rise Time

RPUCLOAD 1s



(EQ. 1)

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