ISL9216IRZ datasheet(28/34 Pages) RENESAS

28 / 34 page

ISL9216, ISL9217

FN6488 Rev 1.00

Page 28 of 34

November 2, 2007

When data is clocked into the ISL9216 through the I2C port, it is

immediately transferred to the serial cascade port, so both the

ISL9216 and ISL9217 see the slave byte at the same time. After

the 8th slave bit, the device that receives the correct slave byte

sends an acknowledge, while the other device ignores all

subsequent data on the serial port until it receives a stop bit.

However, even though the ISL9216 ignores the data, it still

passes it through to the ISL9217.

The SDAI and SDAO pins of the ISL9217 need to have pull-up

resistors of approximately 4.7k

, since the output drivers are

open-drain devices.

The Discharge Set, Charge Set, and Feature Set configuration

registers are write protected on initial power-up. In order to

write to these registers it is necessary to set a bit to enable

each one. These write enable bits are in the Write Enable

Write the FSETEN bit (Addr 8:bit 7) to “1” to change the data in

the Feature Set register (Address 7).

Write the CHSETEN bit (Addr 8:bit 6) to “1” to change the data

in the Feature Set register (Address 6).

Write the DISSETEN bit (Addr 8:bit 5) to “1” to change the data

in the Feature Set register (Address 5).

The microcontroller can reset these bits back to zero to prevent

inadvertent writes that change the operation of the pack.

Operation State Machine

Figure 16 shows a device state machine which defines how the

ISL9216 and ISL9217 respond to various conditions.

Power Fails and one of the supplies, VCC, VCELL1, VCELL2,

and VCELL3 do not meet minimum voltage requirements

WKUP goes above or below

threshold (edge triggered).

[ISL9217 wake-up requires µC

command to ISL9216].

Or, SLEEP bit is set to ‘0’

I2C interface is disabled. Biasing is disabled.

All registers set to default values (All “0”)

POWER-DOWN STATE

I2C interface is enabled. Biasing is enabled.

Voltage Regulator is enabled.

POWER-UP STATE

Voltage Regulator is ON

Logic and registers are powered by RGO

CFET, DFET, Cell balancing outputs are all off.

(Require external command to turn on)

Charge and discharge current protection

circuits and temperature protection circuits are

active (Default). Overcurrent conditions force

power FETs to turn off. Over-temperature

conditions force power FETs and cell balance

outputs to turn off.

Voltage and temperature monitoring circuits

are awaiting external control.

MAIN OPERATING STATE

Power is applied and all of the supplies, VCC, VCELL1,

VCELL2, and VCELL3 meet minimum voltage requirements

Voltage Regulator is OFF

Biasing is OFF

Logic and registers are powered by VCELL1

CFET, DFET, Cell balancing outputs are all off.

Charge and discharge current protection

circuits all off.

Voltage and temperature monitoring circuits

are off.

I2C communication is active (if VCELL1 voltage

is high enough to operate with external

device.)

SLEEP STATE

SLEEP bit is set to ‘1’

FIGURE 16. DEVICE OPERATION STATE MACHINE

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