ISL6315 datasheet(13/20 Pages) RENESAS

13 / 20 page

ISL6315

FN9222 Rev 1.00

Page 13 of 20

July 18, 2007

In summary, for the ISL6315 to operate, the following

conditions need be met: VCC and PVCC must be greater

than their respective POR thresholds, the voltage at ENLL

must be greater than 0.61V, and VID has to be different than

‘11111’. Once all these conditions are met, the controller

immediately initiates a soft start sequence.

SOFT-START

The soft-start function allows the converter to bring up the

output voltage in a controlled fashion, resulting in a linear

ramp-up. Following a delay of 16 PHASE clock cycles (about

s) between enabling the chip and the start of the ramp,

the output voltage progresses at a fixed rate of 12.5mV per

16 PHASE clock cycles.

Thus, the soft-start period (not including the 70

s wait) up to

a given voltage, VDAC, can be approximated by the following

equation

where VDAC is the DAC-set VID voltage, and fS is the

switching frequency (typically 222kHz).

The ISL6315 also has the ability to start up into a pre-charged

output, without causing any unnecessary disturbance. The FB

pin is monitored during soft-start, and should it be higher than

the equivalent internal ramping reference voltage, the output

drives hold both MOSFETs off. Once the internal ramping

reference exceeds the FB pin potential, the output drives are

enabled, allowing the output to ramp from the pre-charged

level to the final level dictated by the DAC setting. Should the

output be pre-charged to a level exceeding the DAC setting,

the output drives are enabled at the end of the soft-start

period, leading to an abrupt correction in the output voltage

down to the DAC-set level.

FREQUENCY COMPENSATION

The ISL6315 multiphase converter behaves in a similar

manner to a voltage-mode controller. This section highlights

the design consideration for a voltage-mode controller requiring

external compensation. To address a broad range of

applications, a type-3 feedback network is recommended.

Figure 8 highlights the voltage-mode control loop for a

synchronous-rectified buck converter, applicable, with a small

number of adjustments, to the multiphase ISL6315 circuit. The

output voltage (VOUT) is regulated to the reference voltage,

VREF, level. The error amplifier output (COMP pin voltage) is

compared with the oscillator (OSC) modified saw-tooth wave to

provide a pulse-width modulated wave with an amplitude of VIN

at the PHASE node. The PWM wave is smoothed by the output

filter (L and C). The output filter capacitor bank’s equivalent

series resistance is represented by the series resistor E.

The modulator transfer function is the small-signal transfer

function of VOUT/VCOMP. This function is dominated by a DC

gain, given by dMAXVIN/VOSC, and shaped by the output

filter, with a double pole break frequency at FLC and a zero at

FCE. For the purpose of this analysis, L and D represent the

individual channel inductance and its DCR divided by 2

(equivalent parallel value of the two output inductors), while C

TSS

VDAC 1280



---------------------------------

(EQ. 7)

FIGURE 7. SOFT-START WAVEFORMS FOR ISL6315-BASED

MULTIPHASE CONVERTER

ENLL (5V/DIV)

VOUT (0.5V/DIV)

GND>

OUTPUT PRECHARGED

BELOW DAC LEVEL

OUTPUT PRECHARGED

ABOVE DAC LEVEL

FIGURE 8. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

E/A

VREF

COMP

VIN

PWM

CIRCUIT

HALF-BRIDGE

DRIVE

OSCILLATOR

EXTERNAL CIRCUIT

ISL6315

VOUT

VOSC

UGATE

PHASE

LGATE

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