ISL6442 datasheet(13/17 Pages) RENESAS

13 / 17 page

ISL6442

FN9204 Rev 2.00

Page 13 of 17

Oct 31, 2008

The modulator transfer function is the small-signal transfer

function of VOUT/VCOMP. This function is dominated by a DC

gain, given by dMAXVIN/VOSC, and shaped by the output filter,

with a double pole break frequency at FLC and a zero at FCE.

For the purpose of this analysis, L and D represent the channel

inductance and its DCR, while C and E represent the total output

capacitance and its equivalent series resistance.

The compensation network consists of the error amplifier (internal

to the ISL6442) and the external R1-R3, C1-C3 components. The

goal of the compensation network is to provide a closed loop

transfer function with high 0dB crossing frequency (F0; typically

0.1 to 0.3 of FSW) and adequate phase margin (better than 45°).

Phase margin is the difference between the closed loop phase at

F0dB and 180°. The equations that follow relate the compensation

network’s poles, zeros and gain to the components (R1, R2, R3,

C1, C2, and C3) in Figure 14. Use the following guidelines for

locating the poles and zeros of the compensation network:

1. Select a value for R1 (1k

 to 5k, typically). Calculate

value for R2 for desired converter bandwidth (F0). If setting

the output voltage via an offset resistor connected to the FB

pin, Ro in Figure 14, the design procedure can be followed

as presented in Equation 12.

2. Calculate C1 such that FZ1 is placed at a fraction of the FLC, at

0.1 to 0.75 of FLC (to adjust, change the 0.5 factor to desired

number). The higher the quality factor of the output filter and/or

the higher the ratio FCE/FLC, the lower the FZ1 frequency (to

maximize phase boost at FLC).

3. Calculate C2 such that FP1 is placed at FCE.

4. Calculate R3 such that FZ2 is placed at FLC. Calculate C3 such

that FP2 is placed below FSW (typically, 0.5 to 1.0 times

FSW). FSW represents the switching frequency. Change the

numerical factor to reflect desired placement of this pole.

Placement of FP2 lower in frequency helps reduce the gain

of the compensation network at high frequency, in turn

reducing the HF ripple component at the COMP pin and

minimizing resultant duty cycle jitter.

It is recommended a mathematical model is used to plot the

loop response. Check the loop gain against the error

amplifier’s open-loop gain. Verify phase margin results and

adjust as necessary. The following equations describe the

frequency response of the modulator (GMOD), feedback

compensation (GFB) and closed-loop response (GCL):

where:

FIGURE 14. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

E/A

VREF

COMP

VIN

PWM

CIRCUIT

HALF-BRIDGE

DRIVE

OSCILLATOR

EXTERNAL CIRCUIT

ISL6442

VOUT

VOSC

UGATE

LGATE

PHASE

FLC





---------------------------

(EQ. 10)

FCE

 CE



------------------------

(EQ. 11)

VOSC R1 F0



dMAX VIN FLC



---------------------------------------------

(EQ. 12)

 R2 0.5 F





------------------------------------------------

(EQ. 13)

 R2 C1 F

–





---------------------------------------------------------

(EQ. 14)

FSW

FLC

------------ 1

–

----------------------

 R3 0.7 F





-------------------------------------------------

(EQ. 15)

GMOD f

dMAX VIN



VOSC

------------------------------

1s f

 EC



1s f

 ED

 C



2 f LC



----------------------------------------------------------------------------------------



(EQ. 16)

GFB f

1s f

 R2 C1



 R1 C1 C2





------------------------------------------------------



1s f

 R1 R3

 C3



1s f

 R3 C3



 1s f

 R2

C1 C2



C1 C2

----------------------













-----------------------------------------------------------------------------------------------------------------------------



(EQ. 17)

GCL f

GMOD f GFB f



(EQ. 18)



 fj



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