ISL8103 datasheet(21/28 Pages) RENESAS

21 / 28 page

ISL8103

FN9246 Rev 1.00

Page 21 of 28

July 21, 2008

Compensation

The two opposing goals of compensating the voltage

regulator are stability and speed. Depending on whether the

regulator employs the optional load-line regulation as

described in

“Load-Line (Droop) Regulation” on page 12,

there are two distinct methods for achieving these goals.

Compensating the Load-Line Regulated Converter

The load-line regulated converter behaves in a similar

manner to a peak current mode controller because the two

poles at the output filter L-C resonant frequency split with the

introduction of current information into the control loop. The

final location of these poles is determined by the system

function, the gain of the current signal, and the value of the

compensation components, R2 and C1.

Since the system poles and zero are affected by the values

of the components that are meant to compensate them, the

solution to the system equation becomes fairly complicated.

Fortunately, there is a simple approximation that comes very

close to an optimal solution. Treating the system as though it

were a voltage-mode regulator, by compensating the L-C

poles and the ESR zero of the voltage mode approximation,

yields a solution that is always stable with very close to ideal

transient performance.

The feedback resistor, R1, has already been chosen as

outlined in “Load-Line (Droop) Regulation” on page 12.

Select a target bandwidth for the compensated system, F0.

The target bandwidth must be large enough to assure

adequate transient performance, but smaller than 1/3 of the

per-channel switching frequency. The values of the

compensation components depend on the relationships of

F0 to the L-C double pole frequency and the ESR zero

frequency. For each of the following three, there is a

separate set of equations for the compensation components.

In Equation 28, L is the per-channel filter inductance divided

by the number of active channels; C is the sum total of all

output capacitors; ESR is the equivalent series resistance of

the bulk output filter capacitance; and VPP is the peak-to-

peak sawtooth signal amplitude as described in the

“Electrical Specifications” on page 5.

Once selected, the compensation values in Equations 28

assure a stable converter with reasonable transient

performance. In most cases, transient performance can be

improved by making adjustments to R2. Slowly increase the

value of R2 while observing the transient performance on an

oscilloscope until no further improvement is noted. Normally,

C1 will not need adjustment. Keep the value of C1 from

Equations 28 unless some performance issue is noted.

The optional capacitor C2, is sometimes needed to bypass

noise away from the PWM comparator (see Figure 19). Keep

a position available for C2, and be prepared to install a high

frequency capacitor of between 22pF and 150pF in case any

leading edge jitter problem is noted.

FIGURE 18. TIME CONSTANT MISMATCH BEHAVIOR

V1

VOUT

ITRAN

V2

I

FIGURE 19. COMPENSATION CONFIGURATION FOR

LOAD-LINE REGULATED ISL8103 CIRCUIT

ISL8103

COMP

VDIFF

C2 (Optional)





--------------------------- F0

 F

0 VOSC







0.66 VIN



------------------------------------------------------------



0.66 VIN



 V

OSC R1 f0





-------------------------------------------------

Case 1:





--------------------------- F0

 CESR



---------------------------------



VOSC 2

2 F

2 LC



 

0.66 VIN



----------------------------------------------------------------



0.66 VIN





2 F

2 V

OSC R1







--------------------------------------------------------------------------------

Case 2:

(EQ. 28)

 C ESR



---------------------------------

 F

0 VOSC L





0.66 VIN ESR



-----------------------------------------------



0.66 VIN ESR C





 V

OSC R1 F0





---------------------------------------------------------------

Case 3:

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