AM29BDS640G datasheet(19/65 Pages) SPANSION

19 / 65 page

October 1, 2003 25903C1

Am29BDS640G

Prelimin ary

Current is reduced for the duration of the RESET# pulse. When RESET# is held

at VSS ± 0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held

at VIL but not within VSS ± 0.2 V, the standby current will be greater.

RESET# may be tied to the system reset circuitry. A system reset would thus also

reset the Flash memory, enabling the system to read the boot-up firmware from

the Flash memory.

If RESET# is asserted during a program or erase operation, the device requires

a time of tREADY (during Embedded Algorithms) before the device is ready to read

data again. If RESET# is asserted when a program or erase operation is not ex-

ecuting, the reset operation is completed within a time of tREADY (not during

Embedded Algorithms). The system can read data tRH after RESET# returns to

VIH.

Refer to the AC Characteristics tables for RESET# parameters and to Figure 20,

“Reset Timings,” on page 57 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The outputs are

placed in the high impedance state.

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing

provides data protection against inadvertent writes (refer to Table 13, “Command

Definitions,” on page 37 for command definitions).

The device offers two types of data protection at the sector level:

The sector lock/unlock command sequence disables or re-enables both pro-

gram and erase operations in any sector.

When WP# is at VIL, sectors 0 and 1 (bottom boot) or sectors 132 and 133

(top boot) are locked.

When ACC is at VIL, all sectors are locked.

The following hardware data protection measures prevent accidental erasure or

programming, which might otherwise be caused by spurious system level signals

during VCC power-up and power-down transitions, or from system noise.

Write Protect (WP#)

The Write Protect (WP#) input provides a hardware method of protecting data

without using VID.

If the system asserts VIL on the WP# pin, the device disables program and erase

functions in sectors 0 and 1 (bottom boot) or sectors 132 and 133 (top boot).

If the system asserts VIH on the WP# pin, the device reverts to whether the two

outermost 8K Byte boot sectors were last set to be protected or unprotected.

Note that the WP# pin must not be left floating or unconnected; inconsistent be-

havior of the device may result.

Low VCC Write Inhibit

When VCC is less than VLKO, the device does not accept any write cycles. This pro-

tects data during VCC power-up and power-down. The command register and all

internal program/erase circuits are disabled, and the device resets to reading

array data. Subsequent writes are ignored until VCC is greater than VLKO. The sys-

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