4

ATR2406 [Preliminary]

4779F–ISM–09/04

Functional Description

Receiver

The RF signal at RF_IN is differently fed through the LNA to the image rejection mixer

IR_MIXER driving the integrated LowIF bandpass filter. The IF frequency is

864 kHz.The limiting IF_AMP with an integrated RSSI function feeds the signal to the

digital demodulator DEMOD. No tuning is required. Datasling is handled internally.

Clock Recovery

For 1152 kBit/s data rate the receiver has a clock recovery function on-chip.

The receiver includes a clock recovery circuit which regenerates the clock out of the

received data. The advantage is that this recovered clock is synchronous to the clock of

the transmitting device (and thus to the transmitted data) which allows to reduce the

load of the processing microcontroller significantly.

The falling edge of the clock gives the optimal sampling position for the RX_Data signal

so at this event the data must be sampled by the microcontroller. The recovered clock is

available at pin 6.

Transmitter

The transmit data at TX_DATA is filtered by an integrated Gaussian Filter GF and fed to

the fully integrated VCO operating at twice the output frequency. After modulation the

signal is frequency-divided by 2 and fed to the internal preamplifier PA. This preamplifier

supplies typically +4 dBm output power at TX_OUT.

A ramp-signal generator RAMP_GEN, providing a ramp signal at RAMP_OUT for the

external power amplifier, is integrated. The slope of the ramp signal is controlled inter-

nally so that spurious requirements are fulfilled.

Synthesizer

The IR_MIXER, the PA and the programmable counter PC are driven by the fully inte-

grated VCO, using on-chip inductors and varactors. The output signal is frequency

divided to supply the desired frequency to the TX_DRIVER, 0/90 degree phase shifter

fo r t he IR _M IX ER a n d t o be u s ed b y t he P C fo r th e ph as e d e t e c t o r P D

(f

Power Supply

An integrated bandgap-stabilized voltage regulator for use with an external low-cost

PNP transistor is implemented. Multiple power-down and current saving modes are

provided.