ISL9440 datasheet(13/20 Pages) RENESAS

13 / 20 page

ISL9440, ISL9440A, ISL9441

FN6383 Rev 2.00

Page 13 of 20

February 9, 2015

Functional Description

General Description

The ISL9440, ISL9440A and ISL9441 are integrate control

circuits for three synchronous buck converters and one linear

controller. The three synchronous bucks operate out of phase

to substantially reduce the input ripple and thus reduce the

input filter requirements. The chip has 3 control lines (EN1,

EN2 and EN3), which provide independent control for each of

the synchronous buck outputs.

The buck PWM controllers employ free-running frequency of

300kHz (ISL9440 and ISL9441) and 600kHz (ISL9440A). The

current mode control scheme with an input voltage

feed-forward ramp input to the modulator provides an excellent

rejection of input voltage variations and provides simplified

loop compensations.

The linear controller can drive either a PNP or PFET to provide

ultra low-dropout regulation with programmable voltages.

Internal 5V Linear Regulator (VCC_5V)

All ISL9440, ISL9440A and ISL9441 functions are internally

powered from an on-chip, low dropout 5V regulator. The

maximum regulator input voltage is 24V. Bypass the regulator’s

output (VCC_5V) with a 4.7µF capacitor to ground. The

dropout voltage for this LDO is typically 600mV, so when VIN is

greater than 5.6V, VCC_5V is typically 5V. The ISL9440,

ISL9440A and ISL9441 also employ an undervoltage lockout

circuit that disables both regulators when VCC_5V falls below

4.4V.

The internal LDO can source over 60mA to supply the IC,

power the low side gate drivers and charge the external boot

capacitor. When driving large FETs especially at 300kHz

(ISL9440, ISL9441)/600kHz (ISL9440A) frequency, little or no

regulator current may be available for external loads.

For example, a single large FET with 15nC total gate charge

requires 15nC x 300kHz = 4.5mA (15nC x 600kHz = 9mA).

Also, at higher input voltages with larger FETs, the power

dissipation across the internal 5V will increase. Excessive

dissipation across this regulator must be avoided to prevent

junction temperature rise. Larger FETs can be used with 5V

±10% input applications. The thermal overload protection

circuit will be triggered, if the VCC_5V output is short-circuit.

Connect VCC_5V to VIN for 5V ±10% input applications.

Digital Enable Signals

The typical applications for the ISL9440, ISL9440A and

ISL9441 are using digital sequencing controllers for the power

rails. Using a digital enable rather than an analog soft-start

provides a well controlled method for sequencing up and down

on the power rails.

Soft-Start Operation

The ISL9440, ISL9440A and ISL9441 have a fixed soft-start

time, 1.7ms (TYP). PGOOD will not toggle to high until

soft-start is done and all the four outputs are up and in

regulations.

Output Voltage Programming

The ISL9440, ISL9440A and ISL9441 use a precision internal

reference voltage to set the output voltage. Based on this

internal reference, the output voltage can thus be set from 0.8V

up to a level determined by the input voltage, the maximum

duty cycle, and the conversion efficiency of the circuit.

A resistive divider from the output to ground sets the output

voltage of either PWM channel. The center point of the divider

shall be connected to FBx pin. The output voltage value is

determined by Equation 1.

where R1 is the top resistor of the feedback divider network

and R2 is the resistor connected from FBx to ground.

Out-of-Phase Operation

To reduce input ripple current, Channel 1 and Channel 2 operate

180° out-of-phase, Channel 3 keeps 0 phase degree with

Channel 1. Channel 1 and Channel 2 typically output higher load

compared to Channel 3 because of their stronger drivers. This

reduces the input capacitor ripple current requirements, reduces

power supply-induced noise, and improves EMI. This effectively

helps to lower component cost, save board space and reduce

EMI.

Triple PWMs typically operate in-phase and turn on both upper

FETs at the same time. The input capacitor must then support the

instantaneous current requirements of the three switching

regulators simultaneously, resulting in increased ripple voltage

and current. The higher RMS ripple current lowers the efficiency

due to the power loss associated with the ESR of the input

capacitor. This typically requires more low-ESR capacitors in

parallel to minimize the input voltage ripple and ESR-related

losses, or to meet the required ripple current rating.

With synchronized out-of-phase operation, the high-side

MOSFETs turn on 180° out-of-phase. The instantaneous input

current peaks of both regulators no longer overlap, resulting in

reduced RMS ripple current and input voltage ripple. This reduces

the required input capacitor ripple current rating, allowing fewer or

less expensive capacitors, and reducing the shielding

requirements for EMI. The typical operating curves show the

synchronized 180° out-of-phase operation.

Input Voltage Range

The ISL9440, ISL9440A and ISL9441 are designed to operate

from input supplies ranging from 4.5V to 24V.

For 5V ±10% input applications, ISL9441 is suggested. The

reason is that VIN and VCC_5V Pin should be tied together for

this input application. The early warning function will pull

PGOOD and RST low for ISL9440 and ISL9440A. ISL9441

has not been implemented with early warning function.

VOUTx

0.8V

R1 R2

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(EQ. 1)

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