ISL6563CRZ datasheet(6/20 Pages) RENESAS

6 / 20 page

ISL6563

FN9126 Rev 8.00

Page 6 of 20

Jun 10, 2010

Functional Pin Description

VCC (Pin 8)

Bias supply for the IC’s small-signal circuitry. Connect this

pin to a 5V supply and locally decouple using a quality 0.1µF

ceramic capacitor.

PVCC (Pin 16)

Power supply pin for the MOSFET drives. Connect this pin to

a 5V supply and locally decouple using a quality 1µF

ceramic capacitor.

GND and PGND (Pins 25 and 14)

Connect these pins to the circuit ground using the shortest

possible paths. All internal small-signal circuitry is

referenced to the GND pin. LGATE drive is referenced to the

PGND pin.

VID0-4 (Pins 2, 1, 24-22)

Voltage identification inputs from microprocessor. These pins

respond to TTL logic thresholds. The ISL6563 decodes the

VID inputs to establish the output voltage; see VID Tables for

correspondence between DAC codes and output voltage

settings. These pins are internally pulled high, to

approximately 1.2V, by 40µA (typically) internal current

sources; the internal pull-up current decrease to 0 as the VID

voltage approaches the internal pull-up voltage. All VID pins

are compatible with external pull-up voltages not exceeding

the IC’s bias voltage.

DACSEL/VID5 (Pin 3)

If VRM10 pin is grounded, DACSEL/VID5 represents the 6th

voltage identification input from the VRM10-compliant

microprocessor, otherwise known as VID5. If VRM10 pin is

open or pulled high, DACSEL/VID5 selects the compliance

standard for the internal DAC: pulled to ground it encodes the

DAC with AMD Hammer VID codes, while left open or pulled

high, it encodes the DAC with Intel VRM9.0 codes.

VRM10 (Pin 4)

This pin selects VRM10.0 DAC compliance when grounded.

Left open, it allows selection of either VRM9.0 or Hammer

DAC compliance via DACSEL pin.

ENLL (Pin 21)

This pin is a precision-threshold (approximately 0.6V) enable

pin. Held low, this pin disables controller operation. Pulled

high, the pin enables the controller for operation.

FB and COMP (Pins 6, 5)

The internal error amplifier’s inverting input and output

respectively. These pins are connected to the external

network used to compensate the regulator’s feedback loop.

An internal current source injects the average current

sampled through RISEN into the FB pin. Pulling COMP to

ground through an impedance lower than 15

 disables the

controller (same effect as ENLL pulled low).

ISEN (Pin 7)

This pin is used to close the current-feedback loop and set the

overcurrent protection threshold. A resistor connected between

this pin and VCC has a voltage drop forced across it equal to

that sampled across the lower MOSFET’s rDS(ON) during

approximately the middle of its conduction interval. The

resulting current through this resistor is used for channel

current balancing, overcurrent protection and is sourced to the

FB pin for load-line regulation. The voltage across the RISEN

resistor is time multiplexed between the two channels.

Use Equation 1 to select the proper RISEN resistor:

where:

rDS(ON) = lower MOSFET drain-source ON-resistance ()

IOUT = channel maximum output current (A)

Read ‘Current Feedback’ paragraph for more information.

UGATE1, 2 (Pins 19, 12)

Connect these pins to the upper MOSFETs’ gates. These

pins are used to control the upper MOSFETs and are

monitored for shoot-through prevention purposes. Maximum

individual channel duty cycle is limited to 66%.

BOOT1, 2 (Pins 20, 11)

These pins provide the bias voltage for the upper MOSFETs’

drives. Connect these pins to appropriately-chosen external

bootstrap capacitors. Internal bootstrap diodes connected to

the PVCC pins provide the necessary bootstrap charge.

PHASE1, 2 (Pins 18, 13)

Connect these pins to the sources of the upper MOSFETs.

These pins are the return path for the upper MOSFETs’ drives.

LGATE1, 2 (Pins 17, 15)

These pins are used to control the lower MOSFETs and are

monitored for shoot-through prevention purposes. Connect

these pins to the lower MOSFETs’ gates.

OFS (Pin 9)

This pin is used to create an adjustable output voltage offset.

For no offset, leave this pin open. For negative offset, connect

an R’OFS resistor from this pin to VCC and size it according to

Equation 2:

where:

VOFFSET = desired output voltage offset magnitude (mV)

For positive output voltage offset, connect an ROFS resistor

from this pin to GND, sizing it according to Equation 3:

RISEN

rDS ON

 IOUT



A

------------------------------------------

(EQ. 1)



OFS

1500

VOFFSET

--------------------------



(EQ. 2)

ROFS

500

VOFFSET

--------------------------



(EQ. 3)

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