HIP9011ABZ datasheet(3/11 Pages) RENESAS

3 / 11 page

HIP9011

FN4367 Rev 2.00

Page 3 of 11

January 6, 2006

Absolute Maximum Ratings

Thermal Information

DC Logic Supply, VDD . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V

Output Voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V

Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V Max

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 125oC

Thermal Resistance (Typical, Note 1)

JA (oC/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

120

Maximum Power Dissipation, PD

For TA = -40oC to 70oC . . . . . . . . . . . . . . . . . . . . . . . 400mW Max

For TA = 70oC to 125oC, Derate Linearly at . . . . . . . . . . 6mW/oC

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range, TSTG . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

At a Distance 1/16

1/32 inch, (1.59 0.79mm) from Case for

10s Max. (SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

VDD = 5V 5%, GND = 0V, Clock Frequency 4MHz 0.1%, TA = -40oC to 125oC,

Unless Otherwise Specified

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

DC ELECTRICAL SPECIFICATIONS

Quiescent Supply Current

IDD

VDD = 5.25V, GND = 0V

5.0

8.0

Midpoint Voltage, Pin 3

VMID

VDD = 5.0V, IL = 2mA Source

2.3

2.45

2.55

Midpoint Voltage, Pin 3

VMID

VDD = 5.0V, IL = 0mA

2.4

2.5

2.6

Low Input Voltage, Pins INT/HOLD, CS, SI, SCK

VIL

% of VDD

High Input Voltage, Pins INT/HOLD, CS, SI, SCK

VIH

% of VDD

Hysteresis voltage, Pins INT/HOLD, CS, SI, SCK

VHYST

0.85

Internal Pull-Up Current

I Source CS, SI,

SCK, TEST

VDD = 5.0V, Measured at GND

A

Internal Pull-Down Current

I Sink,

INT/HOLD

VDD = 5.0V, Measured at VDD

--50

A

Low Level Output, Pin SO

VOL

ISOURCE = 1.6mA, VDD = 5.0V

0.01

0.30

High Level Output, Pin SO

VOH

ISINK = 200A, VDD = 5.0V

4.8

4.9

5.0

Three-State Leakage Pin SO

Measured at GND; VDD = 5.0V

10

A

Low Level Output, Pin 10, OSCOUT

VOL

ISOURCE = 500A; VDD = 5.0V

1.5

High Level Output, Pin 10, OSCOUT

VOH

ISINK = -500A; VDD = 5.0V

4.4

SPI BUS INTERFACE

AC Parametrics

CS Falling to SCLK Rising

tCCH

CS Rising to SCLK Falling

tCCL

SCLK Low

tPWL

SCLK High

tPWH

SCLK Falling to CS Rising

tSCCH

Data High Setup Time

tSUH

Data Low Setup Time

tSUL

Data High Hold Time

tHH

Data Low Hold Time

tHL

Min Time Between 2 Programmed Words

tCSH

200

CS Rising to INT/Hold Rising

tCIH

s

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