DSPIC30F6014 datasheet(64/222 Pages) MICROCHIP

64 / 222 page

dsPIC30F6011/6012/6013/6014

DS70117C-page 62

Preliminary

 2004 Microchip Technology Inc.

A parallel I/O (PIO) port that shares a pin with a periph-

eral is, in general, subservient to the peripheral. The

peripheral’s output buffer data and control signals are

provided to a pair of multiplexers. The multiplexers

select whether the peripheral or the associated port

has ownership of the output data and control signals of

the I/O pad cell. Figure 8-2 shows how ports are shared

with other peripherals and the associated I/O cell (pad)

to which they are connected. Table 8-2 through

Table 8-9 show the formats of the registers for the

shared ports, PORTB through PORTG.

FIGURE 8-2:

BLOCK DIAGRAM OF A SHARED PORT STRUCTURE

8.2

Configuring Analog Port Pins

The use of the ADPCFG and TRIS registers control the

operation of the A/D port pins. The port pins that are

desired as analog inputs must have their correspond-

ing TRIS bit set (input). If the TRIS bit is cleared (out-

put), the digital output level (VOH or VOL) will be

converted.

When reading the Port register, all pins configured as

analog input channels will read as cleared (a low level).

Pins configured as digital inputs will not convert an ana-

log input. Analog levels on any pin that is defined as a

digital input (including the ANx pins) may cause the

input buffer to consume current that exceeds the

device specifications.

Note:

The actual bits in use vary between

devices.

WR LAT +

TRIS Latch

I/O Pad

WR Port

Data Bus

Data Latch

Read LAT

Read Port

Read TRIS

WR TRIS

Peripheral Output Data

Output Enable

Peripheral Input Data

I/O Cell

Peripheral Module

Peripheral Output Enable

PIO Module

Output Multiplexers

Output Data

Input Data

Peripheral Module Enable

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