TLE 4727

Datasheet

21

2005-07-20

Optimizing Noise Immunity

Unused inputs should always be wired to proper voltage levels in order to obtain highest

possible noise immunity.

To prevent crossconduction of the output stages the TLE 4727 uses a special break

before make timing of the power transistors. This timing circuit can be triggered by short

glitches (some hundred nanoseconds) at the Phase inputs causing the output stage to

become high resistive during some microseconds. This will lead to a fast current decay

during that time. To achieve maximum current accuracy such glitches at the Phase

inputs should be avoided by proper control signals.

To lower EMI a ceramic capacitor of max. 3 nF is advisable from each output to GND.

Thermal Shut Down

To protect the circuit against thermal destruction, thermal shut down has been

implemented.

Error Monitoring

The error output signals with low-potential one of the following errors:

overtemperature

implemented as pre-alarm; appears approximately 20 K before

thermal shut down.

short circuit

a connection of one output to GND for longer than 30

µs sets an

internal error flipflop. A phase change-over of the affected bridge

resets the flipflop. Being a separate flipflop for each bridge, the

error can be located in such way.

underload

the recirculation of the inductive load is watched. If there is no

recirculation after a phase change-over, the internal error flipflop is

set. Additionally an error is signaled after a phase change-over

during hold-mode.