ISL98002 datasheet(21/28 Pages) RENESAS

21 / 28 page

ISL98002

FN6535 Rev. 0.00

Page 21 of 28

March 26, 2008

preventing any composite sync edges, equalization pulses,

or Macrovision signals from corrupting the black data and

potentially adding a small error in the ABLC™ accumulator.

After the trailing edge of HSYNC, the start of ABLC™ is

delayed by the number of pixels specified in registers 0x14

and 0x15. After that delay, the number of pixels specified

by register 0x17[3:2] are averaged together and added to

the ABLC™’s accumulator. The accumulator stores the

average black levels for the number of lines specified by

DAC value.

The default values provide excellent results with offset

stability and absolute accuracy better than 1 ADC LSB for

most input signals.

ADC

The ISL98002 features 3 fully differential, high-speed 8-bit

ADCs.

Clock Generation

A Digital Phase Lock Loop (DPLL) is employed to generate

the pixel clock frequency. The HSYNC input and the external

XTAL provide a reference frequency to the PLL. The PLL

then generates the pixel clock frequency that is equal to the

incoming HSYNC frequency times the HTOTAL value

programmed into registers 0x0E and 0x0F.

The stability of the clock is very important and correlates

directly with the quality of the image. During each pixel time

transition, there is a small window where the signal is

slewing from the old pixel amplitude and settling to the new

pixel value. At higher frequencies, the pixel signal transitions

at a faster rate, which makes the stable pixel time even

smaller. Any jitter in the pixel clock reduces the effective

stable pixel time and thus the sample window in which pixel

sampling can be made accurately.

Sampling Phase

The ISL98002 provides 64 low-jitter phase choices per pixel

period, allowing the firmware to precisely select the optimum

sampling point. The sampling phase register is 0x10.

HSYNC Slicer

To further minimize jitter, the HSYNC inputs are treated as

analog signals, and brought into a precision slicer block with

thresholds programmable in 400mV steps with 240mV of

hysteresis, and a subsequent digital glitch filter that ignores

any HSYNC transitions within 100ns of the initial transition.

This processing greatly increases the AFE’s rejection of

ringing and reflections on the HSYNC line and allows the

AFE to perform well, even with pathological HSYNC signals.

Voltages given previously and in the “HSYNC Slicer” on

page 21 (register description), are with respect to a 3.3V

sync signal at the HSYNCIN input pin. To achieve 5V

compatibility, a 680

 series resistor should be placed

between the HSYNC source and the HSYNCIN input pin.

Relative to a 5V input, the hysteresis will be 240mV*5V/3.3V

= 360mV, and the slicer step size will be 400mV*5V/3.3V =

600mV per step.

SOG Slicer

The SOG input has programmable threshold, 40mV of

hysteresis, and an optional low pass filter that can be used to

remove high frequency video spikes (generated by

overzealous video peaking in a DVD player, for example)

that can cause false SOG triggers. The SOG threshold sets

the comparator threshold relative to the sync tip (the bottom

of the SOG pulse).

SYNC Status and Polarity Detection

The SYNC Status register (0x01) and the SYNC Polarity

(VSYNCIN, HSYNCIN, and SOGIN) and report their status.

However, accurate sync activity detection is always a

challenge. Noise and repetitive video patterns on the Green

channel may look like SOG activity when there actually is no

SOG signal, while non-standard SOG signals and trilevel

sync signals may have amplitudes below the default SOG

slicer levels and not be easily detected. As a consequence,

not all of the activity detect bits in the ISL98002 are correct

under all conditions.

Table 5 on page 22 shows how to use the SYNC Status

source. The firmware should go through the table in the

order shown, stopping at the first entry that matches the

activity indicators in the SYNC Status register.

Final validation of composite sync sources (SOG or

Composite sync on HSYNC) should be done by setting the

Input Configuration register (0x05) to the composite sync

source determined by Table 5, and confirming that the

CSYNC detect bit is set.

The accuracy of the Trilevel Sync Detect bit can be

increased by multiple reads of the Trilevel Sync detect bit.

See “TriLevel Sync Detect” on page 22 for more details.

For best SOG operation, the SOG low pass filter (register

0x04[4] should always be enabled to reject the high

frequency peaking often seen on video signals.

HSYNC and VSYNC Activity Detect

Activity on these bits always indicates valid sync pulses, so

they should have the highest priority and be used even if the

SOG activity bit is also set.

SOG Activity Detect

The SOG Activity Detect bit monitors the output of the SOG

slicer, looking for 64 consecutive pulses with the same

period and duty cycle. If there is no signal on the Green

(or Y) channel, the SOG slicer will clamp the video to a DC

level and will reject any sporadic noise. There should be no

false positive SOG detects if there is no video on Green

(or Y-Channel).

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