X28HC64

FN8109 Rev 4.00

Page 13 of 18

June 27, 2016

FIGURE 16. CE CONTROLLED WRITE CYCLE

FIGURE 17. PAGE WRITE CYCLE

NOTES:

17. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from

another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.

18. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE

or WE controlled write cycle timing.

ADDRESS

CE

WE

OE

DATA IN

DATA OUT

HIGH Z

DATA VALID

WE

OE

LAST BYTE

Byte 0

Byte 1

Byte 2

Byte n

Byte n+1

Byte n+2

CE

ADDRESS

I/O

writes to an unknown address could occur.

Note 17

Note 18