ZL8101

FN7832 Rev 1.00

Page 3 of 36

July 13, 2012

Pin Configuration

ZL8101

(32 LD QFN)

TOP VIEW

DGND

SYNC

SA0

SA1

NC

SCL

SDA

SALRT

VDD

VR

PWMH

SGND

PWML

ISENA

ISENB

NC

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

32

31

30

29

28

27

26

25

9

1011

12

13

1415

16

EXPOSED PADDLE*

*CONNECT TO SGND

Pin Descriptions

PIN

LABEL

TYPE

(Note 3)

DESCRIPTION

1

DGND

PWR

Digital ground. Connect to low impedance contiguous ground plane.

2SYNC

I/O, M

(Note 4)

Clock synchronization input. Used to set the frequency of the internal switch clock, to sync to an external

clock or to output internal clock.

3SA0

I, M

Serial address select pins. Used to assign a unique address for each individual device or to enable certain

management features.

4SA1

5

NC

No Connect. Leave pin open.

6

SCL

I/O

Serial clock. Connect to external host and/or to other ZL devices.

7

SDA

I/O

Serial data. Connect to external host and/or to other ZL devices.

8

SALRT

O

Serial alert. Connect to external host if desired.

9

FC

I

Auto compensation configuration pin. Used to set up auto compensation.

10

V0

I, M

11

V1

12

VMON

I, M

External voltage monitoring (can be used for external driver bias monitoring for Power-Good).

13

DRVCTL

O

External driver enable control output.

14

VTRK

I

Tracking sense input. Used to track an external voltage source.

15

VSEN+

I

Differential Output voltage sense feedback. Connect to positive output regulation point.

16

VSEN-

I

Differential Output voltage sense feedback. Connect to negative output regulation point.

17

NC

No Connect. Leave pin open.

18

ISENB

I

Differential voltage input for current sensing.

19

ISENA

I

Differential voltage input for current sensing. High voltage (DCR).