FT29F040B-120EC datasheet(7/36 Pages) FORCE

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DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register it-

self does not occupy any addressable memor y

location. The register is composed of latches that store

the commands, along with the address and data infor-

mation needed to execute the command. The contents

of the register serve as inputs to the internal state ma-

chine. The state machine outputs dictate the function of

the device. The appropriate device bus operations

table lists the inputs and control levels required, and the

resulting output. The following subsections describe

each of these operations in further detail.

Table 1.

FT29F040B Device Bus Operations

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In

Note: See the “Sector Protection/Unprotection” section. for more information.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to VIL. CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE# should

remain at VIH.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory con-

tent occurs during the power transition. No command is

necessary in this mode to obtain array data. Standard

microprocessor read cycles that assert valid addresses

on the device address inputs produce valid data on the

device data outputs. The device remains enabled for

read access until the command register contents are

altered.

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifica-

tions and to the Read Operations Timings diagram for

the timing waveforms. ICC1 in the DC Characteristics

table represents the active current specification for

reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to VIL, and OE# to VIH.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. The Sector Address Tables

indicate the address space that each sector occupies.

A “sector address” consists of the address bits required

to uniquely select a sector. See the “Command Defini-

tions” section for details on erasing a sector or the

entire chip, or suspending/resuming the erase

operation.

After the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in this

mode. Refer to the “Autoselect Mode” and “Autoselect

Command Sequence” sections for more information.

ICC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. The “AC

Characteristics” section contains timing specification

tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status

bits on DQ7–DQ0. Standard read cycle timings and ICC

read specifications apply. Refer to “Write Operation

Status” for more information, and to each AC Charac-

teristics section for timing diagrams.

Standby Mode

When the system is not reading or writing to the device,

it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the

Operation

CE#

OE#

WE#

A0–A20

DQ0–DQ7

Read

AIN

DOUT

Write

AIN

DIN

CMOS Standby

VCC ± 0.5 V

High-Z

TTL Standby

High-Z

Output Disable

High-Z

FT29F040B

Rev 2

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