 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AS7C3364PFS36A Datasheet(PDF) 6 Page - Alliance Semiconductor Corporation |
|
|
|||||||||||||||||||||||||||||
AS7C3364PFS36A Datasheet(HTML) 6 Page - Alliance Semiconductor Corporation |
|
|
6 / 11 page  AS7C3364PFS32A AS7C3364PFS36A ® 2/1/01 Alliance Semiconductor P. 6 of 11 Timing characteristics over operating range *See “Notes” on page 10. Key to switching waveforms Parameter Symbo l –166 –150 –133 –100 Unit Notes * Min Max Min Max Min Max Min Max Clock frequency fMax – 166 – 150 – 133 – 100 MHz Cycle time (pipelined mode) tCYC 6 – 6.7 – 7.5 – 10 – ns Cycle time (flow-through mode) tCYCF 10 –10–12 –12– ns Clock access time (pipelined mode) tCD – 3.5 – 3.8 – 4.0 – 5.0 ns Clock access time (flow-through mode) tCDF – 9 –10–10 –12 ns Output enable LOW to data valid tOE – 3.5 – 3.8 – 4.0 – 5.0 ns Clock HIGH to output Low Z tLZC 0– 0– 0 – 0 – ns 2,3,4 Data output invalid from clock HIGH tOH 1.5 – 1.5 – 1.5 – 1.5 – ns 2 Output enable LOW to output Low Z tLZOE 0– 0– 0 – 0 – ns 2,3,4 Output enable HIGH to output High Z tHZOE – 3.5 – 3.8 – 4.0 – 4.5 ns 2,3,4 Clock HIGH to output High Z tHZC – 3.5 – 3.8 – 4.0 – 5.0 ns 2,3,4 Output enable HIGH to invalid output tOHOE 0– 0– 0 – 0 – ns Clock HIGH pulse width tCH 2.4 – 2.5 – 2.5 – 3.5 – ns 5 Clock LOW pulse width tCL 2.4 – 2.5 – 2.5 – 3.5 – ns 5 Address setup to clock HIGH tAS 1.5 – 1.5 – 1.5 – 2.0 – ns 6 Data setup to clock HIGH tDS 1.5 – 1.5 – 1.5 – 2.0 – ns 6 Write setup to clock HIGH tWS 1.5 – 1.5 – 1.5 – 2.0 – ns 6,7 Chip select setup to clock HIGH tCSS 1.5 – 1.5 – 1.5 – 2.0 – ns 6,8 Address hold from clock HIGH tAH 0.5 – 0.5 – 0.5 – 0.5 – ns 6 Data hold from clock HIGH tDH 0.5 – 0.5 – 0.5 – 0.5 – ns 6 Write hold from clock HIGH tWH 0.5 – 0.5 – 0.5 – 0.5 – ns 6,7 Chip select hold from clock HIGH tCSH 0.5 – 0.5 – 0.5 – 0.5 – ns 6,8 ADV setup to clock HIGH tADVS 1.5 – 1.5 – 1.5 – 2.0 – ns 6 ADSP setup to clock HIGH tADSPS 1.5 – 1.5 – 1.5 – 2.0 – ns 6 ADSC setup to clock HIGH tADSCS 1.5 – 1.5 – 1.5 – 2.0 – ns 6 ADV hold from clock HIGH tADVH 0.5 – 0.5 – 0.5 – 0.5 – ns 6 ADSP hold fromclock HIGH tADSPH 0.5 – 0.5 – 0.5 – 0.5 – ns 6 ADSC hold from clock HIGH tADSCH 0.5 – 0.5 – 0.5 – 0.5 – ns 6 Undefined/don’t care Falling input Rising input |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
