LTC1748CFW datasheet(15/20 Pages) LINER

15 / 20 page

LTC1748

1748fa

Any noise present on the encode signal will result in

additional aperture jitter that will be RMS summed with the

inherent ADC aperture jitter.

In applications where jitter is critical (high input frequen-

cies) take the following into consideration:

1. Differential drive should be used.

2. Use as large an amplitude as possible; if transformer

coupled use a higher turns ratio to increase the

amplitude.

3. If the ADC is clocked with a sinusoidal signal, filter the

encode signal to reduce wideband noise.

4. Balance the capacitance and series resistance at both

encode inputs so that any coupled noise will appear at

both inputs as common mode noise.

APPLICATIO S I FOR ATIO

VDD

LTC1748

1748 F07

BIAS

VDD

ENC

ANALOG INPUT

2V BIAS

1:4

0.1

µF

CLOCK

INPUT

Ω

TO INTERNAL

ADC CIRCUITS

Figure 7. Transformer Driven ENC/ENC

1748 F08a

ENC

VTHRESHOLD = 2V

ENC

0.1

µF

LTC1748

1748 F08b

ENC

130

Ω

3.3V

130

Ω

MC100LVELT22

LTC1748

Ω

Figure 8a. Single-Ended ENC Drive,

Not Recommended for Low Jitter

Figure 8b. ENC Drive Using a CMOS-to-PECL Translator

The encode inputs have a common mode range of 1.8V to

VDD. Each input may be driven from ground to VDD for

single-ended drive.

Maximum and Minimum Encode Rates

The maximum encode rate for the LTC1748 is 80Msps. For

the ADC to operate properly the encode signal should have

a 50% (

±4%) duty cycle. Each half cycle must have at least

6ns for the ADC internal circuitry to have enough settling

time for proper operation. Achieving a precise 50% duty

cycle is easy with differential sinusoidal drive using a

transformer or using symmetric differential logic such as

PECL or LVDS. When using a single-ended encode signal

asymmetric rise and fall times can result in duty cycles that

are far from 50%.

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