STW81100

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7.8.3 VCO Voltage Amplitude Control

The bits A0 and A1 control the voltage swing of the VCO. The following table gives the voltage level ex-

pected on the resonator nodes.

Table 9.

Data transmission from microprocessor to the STW81100 takes place through the 2 wires (SDA and SCL)

reads the data as receiver. The device that controls the data transfer is known as the Master and the oth-

ers as the slave. The master will always initiate the transfer and will provide the serial clock for synchro-

nization.

8.1 General Features

8.1.1 Power ON Reset

The device at Power ON is able to configure itself to a fixed configuration, with all programmable bits set

to factory default setting.

8.1.2 Data Validity

Data changes on the SDA line must only occur when the SCL is LOW. SDA transitions while the clock is

HIGH are used to identify START or STOP condition.

Figure 17.

8.1.3 START condition

A Start condition is identified by a HIGH to LOW transition of the data bus SDA while the clock signal SCL

is stable in the HIGH state. A Start condition must precede any command for data transfer.

Code A[1:0]

Differential output voltage (Vp)

00

1.1

01

1.3

10

1.9

11

2.1

SDA

SCL

CHANGE

DATA

ALLOWED

DATA LINE

STABLE DATA

VALID

SDA

SCL

CHANGE

DATA

ALLOWED

DATA LINE

STABLE DATA

VALID